8@(  %,embedfire,lubancat-1rockchip,rk35667EmbedFire LubanCat 1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55psci%9F@Xer@ cpu@100cpu,arm,cortex-a55psci%9F@Xer@ cpu@200cpu,arm,cortex-a55psci%9F@Xer@ cpu@300cpu,arm,cortex-a55psci%9F@Xer@ l3-cache,cache;H@Zopp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0display-subsystem,rockchip,display-subsystem firmwarescmi ,arm,scmi-smc protocol@14#opp-table-1,operating-points-v2Bopp-200000000   P PB@opp-300000000  P PB@opp-400000000ׄ  P PB@opp-600000000#F  B@opp-700000000)' ~~B@opp-800000000/ B@B@B@hdmi-sound,simple-audio-card0HDMIGi2s`zokaysimple-audio-card,codecsimple-audio-card,cpu pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24m#xin32k ,fixed-clockxin32kdefault#sram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob _ sata-phy/ zdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob ` sata-phy/ zdisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clk=otg Eutmi_wide/NU zdisabled usb2-phyn uhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clk=host usb2-phyusb3-phy Eutmi_wide/NUzokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(usb@fd800000 ,generic-ehci usbzokayusb@fd840000 ,generic-ohci usbzokayusb@fd880000 ,generic-ehci usbzokayusb@fd8c0000 ,generic-ohci usbzokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd[io-domains&,rockchip,rk3568-pmu-io-voltage-domainzokay!syscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru#/clock-controller@fdd20000,rockchip,rk3568-cruxin24m#/< LG axi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- i2cpclk default zokayregulator@1c ,tcs,tcs4525vdd_cpu 50!regulator-state-mem'pmic@20,rockchip,rk809 "rk808-clkout1rk808-clkout2default#@a#o${$$$$$$$$regulatorsDCDC_REG1 vdd_logic pqregulator-state-mem'DCDC_REG2vdd_gpu pqCregulator-state-mem'DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu pqregulator-state-mem'DCDC_REG5vcc_1v8w@w@regulator-state-mem'LDO_REG1vdda0v9_image  Wregulator-state-mem'LDO_REG2 vdda_0v9  regulator-state-mem'LDO_REG3 vdda0v9_pmu  regulator-state-mem LDO_REG4 vccio_acodec2Z2Zregulator-state-mem'LDO_REG5 vccio_sdw@2Zregulator-state-mem'LDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem 2ZLDO_REG7 vcca_1v8w@w@regulator-state-mem'LDO_REG8 vcca1v8_pmuw@w@regulator-state-mem w@LDO_REG9vcca1v8_imagew@w@Xregulator-state-mem'SWITCH_REG1vcc_3v3regulator-state-mem'SWITCH_REG2 vcc3v3_sd^regulator-state-mem'serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,baudclkapb_pclk&%%&default+8 zdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk'defaultB zdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(defaultB zdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)defaultB zdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk*defaultB zdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllerM power-domain@7a+Mpower-domain@8 a,-.Mpower-domain@9  a/01Mpower-domain@10 a234567Mpower-domain@11 a8Mpower-domain@13 a9Mpower-domain@14 a:;<Mpower-domain@15a=>?@AMgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' hjobmmugpugpubus%B/zokayxCvideo-codec@fdea0400,rockchip,rk3568-vpu hvdpu aclkhclkD/ iommu@fdea0800,rockchip,rk3568-iommu@  aclkiface/ Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ZaclkhclksclkN&$% coreaxiahb/ video-codec@fdee0000,rockchip,rk3568-vepu @ aclkhclkE/ iommu@fdee0800,rockchip,rk3568-iommu@ ? aclkiface/ Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d biuciuciu-driveciu-sampleрNreset zdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a hmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refN stmmacethxFGHzokay rgmiioutput #I3 I$<aLsY@defaultJKLMN^g pOmdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22Ostmmac-axi-config{Frx-queues-configGqueue0tx-queues-configHqueue0vop@fe040000 0@vopgamma-lut (%aclkhclkdclk_vp0dclk_vp1dclk_vp2P/ xzokay,rockchip,rk3566-vop<aports port@0 endpoint@2QYport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?  aclkiface/ zokayPdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DpclkdphyR/ apbNx zdisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi EpclkdphyS/ apbNx zdisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -((iahbisfrcecrefdefault TUV/ +xzokayW Xports port@0endpointYQport@1endpointZqos@fe128000,rockchip,rk3568-qossyscon +qos@fe138080,rockchip,rk3568-qossyscon :qos@fe138100,rockchip,rk3568-qossyscon ;qos@fe138180,rockchip,rk3568-qossyscon <qos@fe148000,rockchip,rk3568-qossyscon ,qos@fe148080,rockchip,rk3568-qossyscon -qos@fe148100,rockchip,rk3568-qossyscon .qos@fe150000,rockchip,rk3568-qossyscon 8qos@fe158000,rockchip,rk3568-qossyscon 2qos@fe158100,rockchip,rk3568-qossyscon 3qos@fe158180,rockchip,rk3568-qossyscon 4qos@fe158200,rockchip,rk3568-qossyscon 5qos@fe158280,rockchip,rk3568-qossyscon 6qos@fe158300,rockchip,rk3568-qossyscon 7qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon =qos@fe190280,rockchip,rk3568-qossyscon >qos@fe190300,rockchip,rk3568-qossyscon ?qos@fe190380,rockchip,rk3568-qossyscon @qos@fe190400,rockchip,rk3568-qossyscon Aqos@fe198000,rockchip,rk3568-qossyscon 9qos@fe1a8000,rockchip,rk3568-qossyscon /qos@fe1a8080,rockchip,rk3568-qossyscon 0qos@fe1a8100,rockchip,rk3568-qossyscon 1dfi@fe230000,rockchip,rk3568-dfi#  [pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<KJIHGhsyspmcmsglegacyerr)($aclk_mstaclk_slvaclk_dbipclkauxpci3`F\\\\Tet pcie-phy/T @@Npipe zokay "]legacy-interrupt-controller H\mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b biuciuciu-driveciu-sampleрNresetzokay  ^ default_`abmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c biuciuciu-driveciu-sampleрNreset zdisabledspi@fe300000 ,rockchip,sfc0@ exvclk_sfchclk_sfccdefault zdisabledmmc@fe310000,rockchip,rk3568-dwcmshc1 <{}| L n6 (|zy{}corebusaxiblocktimerzokay  + :default defrng@fe388000,rockchip,rk3568-rng8@po coreahbNm zdisabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ 4<=ALFqFq?C9mclk_txmclk_rxhclk&g HtxNPQ tx-mrx-mx zdisabled i2s@fe410000,rockchip,rk3568-i2s-tdmA 5<EILFqFqGK:mclk_txmclk_rxhclk&gg HrxtxNRS tx-mrx-mxdefault0hijklmnopqrszokay Ri2s@fe420000,rockchip,rk3568-i2s-tdmB 6<MLFqOO;mclk_txmclk_rxhclk&gg HtxrxNTtx-mxdefaulttuvw zdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7SW<mclk_txmclk_rxhclk&gg HtxrxNUV tx-mrx-mx zdisabledpdm@fe440000,rockchip,rk3568-pdmD LZYpdm_clkpdm_hclk&g  Hrxxyz{|}defaultNXpdm-m zdisabledspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk_\&g Htxdefault~ zdisableddma-controller@fe530000,arm,pl330arm,primecellS@  m  apb_pclk %dma-controller@fe550000,arm,pl330arm,primecellU@ m  apb_pclk gi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ /HG i2cpclkdefault  zdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0JI i2cpclkdefault  zdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1LK i2cpclkdefault  zdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2NM i2cpclkdefault  zdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3PO i2cpclkdefault  zdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia gRQspiclkapb_pclk&%% Htxrxdefault   zdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib hTSspiclkapb_pclk&%% Htxrxdefault   zdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic iVUspiclkapb_pclk&%% Htxrxdefault   zdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid jXWspiclkapb_pclk&%% Htxrxdefault   zdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte ubaudclkapb_pclk&%%default+8 zdisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v# baudclkapb_pclk&%%default+8zokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w'$baudclkapb_pclk&%%default+8 zdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x+(baudclkapb_pclk&%% default+8 zdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y/,baudclkapb_pclk&% % default+8 zdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z30baudclkapb_pclk&% % default+8 zdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk {74baudclkapb_pclk&%%default+8 zdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl |;8baudclkapb_pclk&%%default+8 zdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm }?<baudclkapb_pclk&%%default+8 zdisabledthermal-zonescpu-thermal d  tripscpu_alert0 p passivecpu_alert1 $ passivecpu_crit s  criticalcooling-mapsmap0 0 gpu-thermal   tripsgpu-threshold p passivegpu-target $ passivegpu-crit s  criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq s<Lf@ `tsadcapb_pclkNx sdefaultsleep  zokay % <saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]saradcapb_pclkN saradc-apb Wzokay ipwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultB zdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultB zdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultB zdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultB zdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultB zdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultB zdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultB zdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultB zdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultB zdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultB zdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultB zdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultB zdisabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe<"LN u  zokayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe<%LN u  zokayphy@fe870000,rockchip,rk3568-csi-dphyypclk Napbx zdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz / apbN zdisabledRmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ / apbN zdisabledSusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m  #zokayhost-port zokayotg-port zokayusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m  #zokayhost-port zokayotg-port zokaypinctrl,rockchip,rk3568-pinctrlx[ gpio@fdd60000,rockchip,gpio-bank !.    "gpio@fe740000,rockchip,gpio-bankt "cd   gpio@fe750000,rockchip,gpio-banku #ef  @  Igpio@fe760000,rockchip,gpio-bankv $gh  `  gpio@fe770000,rockchip,gpio-bankw %ij   pcfg-pull-up pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmcemmc-bus8   demmc-clk eemmc-cmd feth0eth1flashfspifspi-pins` cgmac0gmac1gmac1m1-miim Jgmac1m1-rx-bus20  Lgpuhdmitxhdmitxm0-cec Vhdmitx-scl Thdmitx-sda Ui2c0i2c0-xfer    i2c1i2c1-xfer   i2c2i2c2m0-xfer  i2c3i2c3m0-xfer i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrckrx ki2s1m0-lrcktx ji2s1m0-sclkrx ii2s1m0-sclktx hi2s1m0-sdi0  li2s1m0-sdi1  mi2s1m0-sdi2  ni2s1m0-sdi3 oi2s1m0-sdo0 pi2s1m0-sdo1 qi2s1m0-sdo2  ri2s1m0-sdo3  si2s2i2s2m0-lrcktx ui2s2m0-sclktx ti2s2m0-sdi vi2s2m0-sdo wi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk xpdmm0-clk1 ypdmm0-sdi0  zpdmm0-sdi1  {pdmm0-sdi2  |pdmm0-sdi3 }pmicpmic_int #pmupwm0pwm0m0-pins 'pwm1pwm1m0-pins (pwm2pwm2m0-pins )pwm3pwm3-pins *pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ _sdmmc0-clk `sdmmc0-cmd asdmmc0-det bsdmmc1sdmmc2spdifspdifm0-tx ~spi0spi0m0-pins0  spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer &uart1uart1m0-xfer   uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac1m1-tx-bus2-level30 Kgmac1m1-rgmii-bus-level3@ Ngmac-txc-level2gmac1m1-rgmii-clk-level2 Mledssys-status-led-pin usbvcc5v0-usb20-host-en vcc5v0-usb30-host-en  chosen ,serial2:1500000n8external-gmac1-clock ,fixed-clocksY@ gmac1_clkin#hdmi-con,hdmi-connectoraportendpointZgpio-leds ,gpio-ledssys-led 8sys_led >heartbeat Ton "defaultusb-5v-regulator,regulator-fixedusb_5vLK@LK@vcc5v0-sys-regulator,regulator-fixed vcc5v0_sysLK@LK@!vcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z2Z!$vcc3v3-pcie-regulator,regulator-fixed vcc3v3_pcie2Z2Z b ." u!]vcc5v0-usb20-host-regulator,regulator-fixed b .Idefaultvcc5v0_usb20_hostvcc5v0-usb30-host-regulator,regulator-fixed b .I defaultvcc5v0_usb30_host interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplysupports-sdbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabellinux,default-triggerdefault-stateenable-active-highstartup-delay-us