8P( 'friendlyarm,nanopi-r2srockchip,rk3328 +7FriendlyElec NanoPi R2Saliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/usb@ff600000/device@2/mmc@ff500000cpus+cpu@0cpuarm,cortex-a53xpsci @+8E@Wdu cpu@1cpuarm,cortex-a53xpsci @+8E@Wdu cpu@2cpuarm,cortex-a53xpsci @+8E@Wdu cpu@3cpuarm,cortex-a53xpsci @+8E@Wdu idle-statespscicpu-sleeparm,idle-statexl2-cachecache@-opp-table-0operating-points-v2 opp-408000000Q~)@:opp-600000000#F~)@opp-8160000000,B@)@opp-1008000000<)@opp-1200000000G()@opp-1296000000M?d )@analog-soundsimple-audio-cardFi2s_yAnalog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem  disabledhdmi-soundsimple-audio-cardFi2s_yHDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk tx!default/ disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrx!defaultsleep/9 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd:io-domains"rockchip,rk3328-io-voltage-domainokayCP^lzgpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+<power-domain@6power-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrx!default / !" disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrx!default /#$% disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrx!default/&okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk!default/' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk!default/(okaypmic@18rockchip,rk805 )xin32krk805-clkout2/*!default(IW+c+o+{++regulatorsDCDC_REG1vdd_log 4 0regulator-state-mem1B@DCDC_REG2vdd_arm 4 0regulator-state-mem1~DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4 vcc_io_332Z2Zregulator-state-mem12ZLDO_REG1vcc_18w@w@regulator-state-mem1w@LDO_REG2 vcc18_emmcw@w@regulator-state-mem1w@LDO_REG3vdd_10B@B@regulator-state-mem1B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk!default/, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk!default/- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrx!default/./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk!default/2M disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk!default/3M disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclk!default/4Mokaypwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk!default/5M disableddma-controller@ff1f0000arm,pl330arm,primecell@X apb_pclkothermal-zonessoc-thermalz6tripstrip-point0ppassivetrip-point1Lpassive7soc-crits criticalcooling-mapsmap070 tsadc@ff250000rockchip,rk3328-tsadc% :$P$tsadcapb_pclk!initdefaultsleep/8998'B .tsadc-apb::G^okayt6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclk'V .saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore'fiommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk;<iommu@ff350800rockchip,iommu5@  F aclkiface<;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreAB ׄׄ=<iommu@ff360480rockchip,iommu 6@6@ JB aclkiface<=vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop' .axiahbdclk> disabledport+ endpoint@0?Diommu@ff373f00rockchip,iommu7?  ; aclkiface disabled>hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #Fiahbisfrcec@hdmi!default /ABC:: disabledports+port@0endpointD?port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk:: disabledphy@ff430000rockchip,rk3328-hdmi-phyC SEysysclkrefoclkrefpclk hdmi_phy"F .cpu-version? disabled@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD::Jx=&'(ABDC"\5H4$WzEEE|n6n6n6ׄn6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk usb480m_phy{WGokayGotg-port?$;<=otg-bvalidotg-idlinestateokayThost-port? > linestateokayUmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-samplenyр'm.resetokay/HIJK!defaultLmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-samplenyр'n.reset disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-samplenyр'o.reset disabledethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac'c .stmmaceth:: okaydfWMM"input/N:rgmiiC/O!defaultNW`$mdiosnps,dwmac-mdio+ethernet-phy@1/P!defaulti'yP )Nethernet@ff550000rockchip,rk3328-gmacU:: macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy'b .stmmaceth:rmii/Q "output disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V'd!default/RSQusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost@ T usb2-phyokayusb@ff5c0000 generic-ehci\  NGUusbokayusb@ff5d0000 generic-ohci]  NGUusbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-samplenyр'h.reset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkhost utmi_wide  # E f okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400  @ @ `   crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclk'D .crypto-rstpinctrlrockchip,rk3328-pinctrl::+ gpio@ff210000rockchip,gpio-bank! 3  bgpio@ff220000rockchip,gpio-bank" 4  )gpio@ff230000rockchip,gpio-bank# 5  fgpio@ff240000rockchip,gpio-bank$ 6  pcfg-pull-up Xpcfg-pull-down `pcfg-pull-none Vpcfg-pull-none-2ma  _pcfg-pull-up-2ma  pcfg-pull-up-4ma  Ypcfg-pull-none-4ma  \pcfg-pull-down-4ma  pcfg-pull-none-8ma  Zpcfg-pull-up-8ma  [pcfg-pull-none-12ma  ]pcfg-pull-up-12ma  ^pcfg-output-high pcfg-output-low pcfg-input-high  Wpcfg-input i2c0i2c0-xfer !VV'i2c1i2c1-xfer !VV(i2c2i2c2-xfer ! VV,i2c3i2c3-xfer !VV-i2c3-pins !VVhdmi_i2chdmii2c-xfer !VVBpdm-0pdmm0-clk !Vpdmm0-fsync !Vpdmm0-sdi0 !Vpdmm0-sdi1 !Vpdmm0-sdi2 !Vpdmm0-sdi3 !Vpdmm0-clk-sleep !Wpdmm0-sdi0-sleep !Wpdmm0-sdi1-sleep !Wpdmm0-sdi2-sleep !Wpdmm0-sdi3-sleep !Wpdmm0-fsync-sleep !Wtsadcotp-pin ! V8otp-out ! V9uart0uart0-xfer ! VX uart0-cts ! V!uart0-rts ! V"uart0-rts-pin ! Vuart1uart1-xfer !VX#uart1-cts !V$uart1-rts !V%uart1-rts-pin !Vuart2-0uart2m0-xfer !VXuart2-1uart2m1-xfer !VX&spi0-0spi0m0-clk !Xspi0m0-cs0 ! Xspi0m0-tx ! Xspi0m0-rx ! Xspi0m0-cs1 ! Xspi0-1spi0m1-clk !Xspi0m1-cs0 !Xspi0m1-tx !Xspi0m1-rx !Xspi0m1-cs1 !Xspi0-2spi0m2-clk !X.spi0m2-cs0 !X1spi0m2-tx !X/spi0m2-rx !X0i2s1i2s1-mclk !Vi2s1-sclk !Vi2s1-lrckrx !Vi2s1-lrcktx !Vi2s1-sdi !Vi2s1-sdo !Vi2s1-sdio1 !Vi2s1-sdio2 !Vi2s1-sdio3 !Vi2s1-sleep !WWWWWWWWWi2s2-0i2s2m0-mclk !Vi2s2m0-sclk !Vi2s2m0-lrckrx !Vi2s2m0-lrcktx !Vi2s2m0-sdi !Vi2s2m0-sdo !Vi2s2m0-sleep` !WWWWWWi2s2-1i2s2m1-mclk !Vi2s2m1-sclk !Vi2sm1-lrckrx !Vi2s2m1-lrcktx !Vi2s2m1-sdi !Vi2s2m1-sdo !Vi2s2m1-sleepP !WWWWWspdif-0spdifm0-tx !Vspdif-1spdifm1-tx !Vspdif-2spdifm2-tx !Vsdmmc0-0sdmmc0m0-pwren !Ysdmmc0m0-pin !Ysdmmc0-1sdmmc0m1-pwren !Ysdmmc0m1-pin !Yhsdmmc0sdmmc0-clk !ZHsdmmc0-cmd ![Isdmmc0-dectn !YJsdmmc0-wrprt !Ysdmmc0-bus1 ![sdmmc0-bus4@ ![[[[Ksdmmc0-pins !YYYYYYYYsdmmc0extsdmmc0ext-clk !\sdmmc0ext-cmd !Ysdmmc0ext-wrprt !Ysdmmc0ext-dectn !Ysdmmc0ext-bus1 !Ysdmmc0ext-bus4@ !YYYYsdmmc0ext-pins !YYYYYYYYsdmmc1sdmmc1-clk ! Zsdmmc1-cmd ! [sdmmc1-pwren ![sdmmc1-wrprt ![sdmmc1-dectn ![sdmmc1-bus1 ![sdmmc1-bus4@ ![[[[sdmmc1-pins ! Y YYYYYYYYemmcemmc-clk !]emmc-cmd !^emmc-pwren !Vemmc-rstnout !Vemmc-bus1 !^emmc-bus4@ !^^^^emmc-bus8 !^^^^^^^^pwm0pwm0-pin !V2pwm1pwm1-pin !V3pwm2pwm2-pin !V4pwmirpwmir-pin !V5gmac-1rgmiim1-pins` ! Z \\Z\\\ \ \Z Z\\ZZZ Z\ZZZZOrmiim1-pins !_]____ _ _] ] V VVVVVgmac2phyfephyled-speed10 !Vfephyled-duplex !Vfephyled-rxm1 !VRfephyled-txm1 !Vfephyled-linkm1 !VStsadc_pintsadc-int ! Vtsadc-pin ! Vhdmi_pinhdmi-cec !VAhdmi-hpd !`Ccif-0dvp-d2d9-m0 !VVVVV V V VVVVVcif-1dvp-d2d9-m1 !VVVVVVVVVVVVbuttonreset-button-pin !Vagmac2ioeth-phy-reset-pin !`Pledslan-led-pin !Vcsys-led-pin !Vdwan-led-pin !Velanlan-vdd-pin !Vipmicpmic-int-l !X*sdsdio-vcc-pin !Xgchosen /serial2:1500000n8gmac-clock fixed-clocksY@ gmac_clkinMkeys gpio-keys/a!defaultkey-reset ;reset b A L2leds gpio-leds /cde!defaultled-0 f ;nanopi-r2s:green:lanled-1 b ;nanopi-r2s:red:sys ^onled-2 f ;nanopi-r2s:green:wansdmmcio-regulatorregulator-gpio l )/g!default vcc_io_sdiow@2Z  voltage w@2Z sdmmc-regulatorregulator-fixed b/h!defaultvcc_sd2Z2Z Lvdd-5vregulator-fixedvdd_5vLK@LK@+vdd-5v-lanregulator-fixed l f/i!default vdd_5v_lan + compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplytx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio