58$(  zkmagic,a95x-z2rockchip,rk3318 +7A95X Z2aliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff550000/mmc@ff500000/mmc@ff510000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci @+8E@Wdu cpu@1cpuarm,cortex-a53xpsci @+8E@Wdu cpu@2cpuarm,cortex-a53xpsci @+8E@Wdu cpu@3cpuarm,cortex-a53xpsci @+8E@Wdu idle-statespscicpu-sleeparm,idle-statexl2-cachecache@-opp-table-0operating-points-v2 opp-408000000Q~)@:opp-600000000#F~)@opp-8160000000,B@)@opp-1008000000<)@opp-1200000000G()@ Fdisabledopp-1296000000M?d )@ Fdisabledanalog-soundsimple-audio-cardMi2sfAnalogFokaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem hdmi-soundsimple-audio-cardMi2sfHDMIFokaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24m@i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrxFokayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrxFokayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx Fdisabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk tx!default/Fokaygpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrx!defaultsleep/9 Fdisabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd4io-domains"rockchip,rk3328-io-voltage-domainFokayCP^lzgpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+7power-domain@6power-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrx!default/Fokayserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrx!default / !" Fdisabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrx!default/#Fokayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk!default/$ Fdisabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk!default/% Fdisabledi2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk!default/& Fdisabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk!default/' Fdisabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrx!default/()*+ Fdisabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk!active/,(Fokaylpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk!active/-(Fokaympwm@ff1b0020rockchip,rk3328-pwm < pwmpclk!default/.( Fdisabledpwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk!default//( Fdisableddma-controller@ff1f0000arm,pl330arm,primecell@3 apb_pclkJthermal-zonessoc-thermalUky0tripstrip-point0_passivetrip-point1(passive1soc-crit8 criticalcooling-mapsmap010 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6D3pcfg-pull-up`Xpcfg-pull-downm`pcfg-pull-none|Vpcfg-pull-none-2ma|_pcfg-pull-up-2ma`pcfg-pull-up-4ma`Ypcfg-pull-none-4ma|\pcfg-pull-down-4mampcfg-pull-none-8ma|Zpcfg-pull-up-8ma`[pcfg-pull-none-12ma| ]pcfg-pull-up-12ma` ^pcfg-output-highpcfg-output-lowpcfg-input-high`Wpcfg-inputi2c0i2c0-xfer VV$i2c1i2c1-xfer VV%i2c2i2c2-xfer  VV&i2c3i2c3-xfer VV'i2c3-pins VVhdmi_i2chdmii2c-xfer VV=pdm-0pdmm0-clkVpdmm0-fsyncVpdmm0-sdi0Vpdmm0-sdi1Vpdmm0-sdi2Vpdmm0-sdi3Vpdmm0-clk-sleepWpdmm0-sdi0-sleepWpdmm0-sdi1-sleepWpdmm0-sdi2-sleepWpdmm0-sdi3-sleepWpdmm0-fsync-sleepWtsadcotp-pin V2otp-out V3uart0uart0-xfer  VXuart0-cts Vuart0-rts Vuart0-rts-pin Vuart1uart1-xfer VX uart1-ctsV!uart1-rtsV"uart1-rts-pinVuart2-0uart2m0-xfer VXuart2-1uart2m1-xfer VX#spi0-0spi0m0-clkXspi0m0-cs0 Xspi0m0-tx Xspi0m0-rx Xspi0m0-cs1 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YYYYYYYYclk-32k-outVMemmcemmc-clk]Nemmc-cmd^Oemmc-pwrenVemmc-rstnoutVemmc-bus1^emmc-bus4@^^^^emmc-bus8^^^^^^^^Ppwm0pwm0-pinVpwm0-pin-pull-upX,pwm1pwm1-pinVpwm1-pin-pull-upX-pwm2pwm2-pinV.pwmirpwmir-pinV/gmac-1rgmiim1-pins` Z \\Z\\\ \ \Z Z\\ZZZ Z\ZZZZrmiim1-pins_]____ _ _] ] V VVVVVgmac2phyfephyled-speed10Vfephyled-duplexVfephyled-rxm1VRfephyled-txm1Vfephyled-linkm1VStsadc_pintsadc-int Vtsadc-pin Vhdmi_pinhdmi-cecV<hdmi-hpd`>cif-0dvp-d2d9-m0VVVVV V V VVVVVcif-1dvp-d2d9-m1VVVVVVVVVVVVirir-intVcledscyx-led-pinVdsdio-pwrseqwifi-enable-hVeusbhost-vbus-drvVotg-vbus-drvVjchosenserial2:1500000n8adc-keys adc-keysabuttonsw@ dbutton-recovery recovery !h ,Bhir-receivergpio-ir-receiver Fb/c!defaultleds gpio-leds/d!defaultled-0 Lon Fb CYX_LEDsdio-pwrseqmmc-pwrseq-simple/e!default ZfIspdif-soundsimple-audio-cardSPDIFsimple-audio-card,cpugsimple-audio-card,codechspdif-outlinux,spdif-dithvccio-1v8-regulatorregulator-fixed fvccio_1v8 uw@ w@ vccio-3v3-regulatorregulator-fixed fvccio_3v3 u2Z 2Z otg-vbus-regulatorregulator-fixed i/j!default fvcc_otg_vbus uLK@ LK@ Csdmmc-regulatorregulator-fixed i/k!default fvcc_sd u2Z 2Z Hvdd-armpwm-regulator l fvdd_arm u~ \   vdd-logpwm-regulator m fvdd_log u      5 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstatussimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shift#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsvref-supplyinterrupt-namesmali-supply#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsphy-supplyfifo-depthmax-frequencybus-widthcap-sd-highspeedvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104cap-mmc-highspeedtx-fifo-depthrx-fifo-depthsnps,txpblphy-modephy-handleclock_in_outassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltgpiosdefault-statereset-gpiosregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ongpioenable-active-highvin-supplypwmsregulator-settling-time-up-usregulator-boot-on