!\8(X$mediatek,mt8195-evbmediatek,mt8195 +!7MediaTek MT8195 evaluation boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@100cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@200cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@300cpuarm,cortex-a55psci#ec3@34FVc@u@ cpu@400cpuarm,cortex-a78psci#f3FVc@u@ cpu@500cpuarm,cortex-a78psci#f3FVc@u@cpu@600cpuarm,cortex-a78psci#f3FVc@u@cpu@700cpuarm,cortex-a78psci#f3FVc@u@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state2 _0Dcpu-retention-barm,idle-state- 0cpu-off-larm,idle-state7 0Hcpu-off-barm,idle-state2 0l2-cache0cacheAXe@wMl2-cache1cacheAXe@wMl3-cachecacheAX e@wMdsu-pmu arm,dsu-pmu[ f kfaildmic-codec dmic-codecr2mt8195-sound kdisabledfixed-factor-clock-13mfixed-factor-clockclk13m(oscillator-26m fixed-clock#clk26moscillator-32k fixed-clock#clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 opp-table-gpuoperating-points-v2Uopp-390000000> hopp-410000000p opp-431000000 opp-4730000001h@ <opp-515000000F <opp-556000000!# Ҧopp-598000000# opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-82000000005 opp-8500000002 @opp-8800000004s qpmu-a55arm,cortex-a55-pmu [pmu-a78arm,cortex-a78-pmu [psci arm,psci-1.0smctimerarm,armv8-timer @[   soc+ simple-businterrupt-controller@c000000 arm,gic-v3): Q   [ ppi-partitionsinterrupt-partition-0f interrupt-partition-1f syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfdosyscon@10003000mediatek,mt8195-pericfgsyscon07pinctrl@10005000mediatek,mt8195-pinctrlPB|iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintQ[)i2c0-pinsDpins ei2c1-pinsEpins  ei2c4-pinsFpinsei2c6-pinsBpinsei2c7-pinspinsenor-pins@pins0 pins1 uart0-pins.pinsbcsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+*power-domain@8+power-domain@9  mfgalt+power-domain@10 power-domain@11 power-domain@12 power-domain@13 power-domain@14power-domain@15 @AK    vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@24 vdec1-0power-domain@27  venc1-larbpower-domain@168$%&'()D vdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17 vppsys1vppsys1-0vppsys1-1power-domain@22 $ wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23  vdec0-0power-domain@25! vdec2-0power-domain@26"  venc0-larbpower-domain@18 ###& vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19power-domain@20power-domain@21Q hdmi_txpower-domain@28$$   img-0img-1+power-domain@29power-domain@30$% ipeipe-0ipe-1power-domain@31(&&&&& cam-0cam-1cam-2cam-3cam-4+power-domain@32 power-domain@33!power-domain@34"power-domain@0power-domain@1power-domain@2power-domain@3power-domain@457 csi_rx_topcsi_rx_top1power-domain@5'  etherpower-domain@6Xn  adspadsp1+power-domain@7 g"n2 audioaudio1audio2audio3watchdog@10007000mediatek,mt8195-wdt*po-syscon@1000c000"mediatek,mt8195-apmixedsyssyscontimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerp[ (pwrap@10024000mediatek,mt8195-pwrapsyscon@|pwrap[  spiwrapB$Rspmi@10027000mediatek,mt8195-spmi p |pmifspmimstE( pmif_sys_ckpmif_tmr_ckspmimst_clk_muxB$Rinfra-iommu@10315000mediatek,mt8195-iommu-infra1PPP[i<mailbox@10320000mediatek,mt8195-gce2@[vxmailbox@10330000mediatek,mt8195-gce3@[vVscp@10500000mediatek,mt8195-scp0Prp|sramcfgl1tcm[ kdisabledWclock-controller@10720000mediatek,mt8195-scp_adspr)dsp@10803000mediatek,mt8195-dsp 0 |cfgsram,Xn)#K adsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h*rxtx+, kdisabledmailbox@10816000mediatek,mt8195-adsp-mboxv`[+mailbox@10817000mediatek,mt8195-adsp-mboxvp[,mt8195-afe-pcm@10890000mediatek,mt8195-audio*[6- audiosysg"#neabcd2) clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp kdisabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart[   baudbuskokaydefault.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart[   baudbus kdisabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart[   baudbus kdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart[   baudbus kdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart[   baudbus kdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart[   baudbus kdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc  mainkokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon0'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+[ parent-clksel-clkspi-clk kdisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap [/0$lvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svs[ main1/(svs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm[*$*0 mainmm kdisabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm[$+N mainmm kdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+[3 parent-clksel-clkspi-clk kdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ [4 parent-clksel-clkspi-clk kdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0[5 parent-clksel-clkspi-clk kdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+[< parent-clksel-clkspi-clk kdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+[= parent-clksel-clkspi-clk kdisabledspi@1101d000mediatek,mt8195-spi-slave[R spiBR kdisabledspi@1101e000mediatek,mt8195-spi-slave[S spiBR kdisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@[/macirq. axiapbmac_mainptp_refrmii_internalmac_cg0''RST' BRSTR*?P2`3s4 kdisabledmdiosnps,dwmac-mdio+stmmac-axi-config2rx-queues-config3queue0 queue1 queue2 queue3 tx-queues-config%;4queue0MYqueue1MYqueue2MYqueue3MYusb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > |macippc ?+[/B sys_ckref_ckmcu_ckg56l z7gkokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci|mac[B,-R$/B$ sys_ckref_ckmcu_ckdma_ckxhci_ckkokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #[ sourcehclksource_cg kdisabledmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $[$ sourcehclksource_cgBR kdisabledmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %[ I sourcehclksource_cgB R kdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'[/0$lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> |macippc[g89B./R$''$ sys_ckref_ckmcu_ckdma_ckxhci_ck z7hlkokayusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-*> |macippc*?+[B0R'' sys_ckref_ckmcu_ckg:l z7ikokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci|mac[B1R' sys_ckkokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-+> |macippc+?+[B2R''  sys_ckref_ckmcu_ckg;l z7jkokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci|mac[B3R'  sys_ckkokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ |pcie-mac[8 <0V#&+K'/ pl_250mtl_26mtl_96mtl_32kperi_26mperi_memBGRg= pcie-phy*mac)`>>>> kdisabledinterrupt-controllerQ)>pcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ |pcie-mac[8$$ $ $ <(WXQ'/ pl_250mtl_26mtl_96mtl_32kperi_26mperi_memBHRg9 pcie-phy*mac)`???? kdisabledinterrupt-controllerQ)?spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2[9o''  spisfaxi+kokaydefault@flash@0jedec,spi-norefuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,1Lusb3-rx-imp@184,2Kusb3-intr@185Jusb3-tx-imp@186,1Iusb3-rx-imp@186,2Husb3-intr@187Gusb2-intr-p0@188,1usb2-intr-p1@188,2usb2-intr-p2@189,1usb2-intr-p3@189,2pciephy-rx-ln1@190,1Spciephy-tx-ln1-nmos@190,2Rpciephy-tx-ln1-pmos@191,1Qpciephy-rx-ln0@191,2Ppciephy-tx-ln0-nmos@192,1Opciephy-tx-ln0-pmos@192,2Npciephy-glb-intr@193Mdp-data@1aclvts1-calib@1bc/lvts2-calib@1d080svs-calib@580d1socinfo-data1@7a0t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+kokayusb-phy@0 ref:t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+kokayusb-phy@0 ref;dsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx0_pll kdisabledydsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx1_pll kdisabledzi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "[A;  maindma+ kdisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "[A;  maindma+kokaydefaultB#i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "[A;  maindma+ kdisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0Ai2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "[C;  maindma+kokaydefaultD#i2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "[C;  maindma+kokaydefaultE#i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "[C;  maindma+ kdisabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"[C;  maindma+ kdisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"[C;  maindma+kokaydefaultF#clock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wPCt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+*kokayusb-phy@0   refda_ref8usb-phy@700  refda_ref GHIintrrx_imptx_imp9t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+kokayusb-phy@0   refda_ref5usb-phy@700  refda_ref JKLintrrx_imptx_imp6phy@11e80000mediatek,mt8195-pcie-phy|sifMNOPQRSGglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1* kdisabled=ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy  unipromp kdisabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@T0[ /jobmmugpuU(* * * * *&core0core1core2core3core4 kdisabledclock-controller@13fbf000mediatek,mt8195-mfgcfgTsyscon@14000000mediatek,mt8195-vppsys0syscon9Vdma-controller@14001000mediatek,mt8195-mdp3-rdma9VQ eW*rX<V V VVVydisplay@14002000mediatek,mt8195-mdp3-fg 9V display@14003000mediatek,mt8195-mdp3-stitch09V0display@14004000mediatek,mt8195-mdp3-hdr@9V@"display@14005000mediatek,mt8195-mdp3-aalP[F9VP *display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz`9V`Q% display@14007000mediatek,mt8195-mdp3-tdshpp9Vp#display@14008000mediatek,mt8195-mdp3-color[I9V$*display@14009000mediatek,mt8195-mdp3-ovl[J9V%*rXdisplay@1400a000mediatek,mt8195-mdp3-padding9V*display@1400b000mediatek,mt8195-mdp3-tcc9Vdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot9VQ +rX*ymutex@1400f000mediatek,mt8195-vpp-mutex[P9V*smi@14010000mediatek,mt8195-smi-sub-common apbsmigals0Y*Zsmi@14011000mediatek,mt8195-smi-sub-common apbsmigals0Y*wsmi@14012000mediatek,mt8195-smi-common-vpp   apbsmigals0gals1*Ylarb@14013000mediatek,mt8195-smi-larb0Z apbsmi*]iommu@14018000mediatek,mt8195-iommu-vpp8[\]^_`abcdefgh[R bclki*Xclock-controller@14e00000mediatek,mt8195-wpesysclock-controller@14e02000mediatek,mt8195-wpesys_vpp0 clock-controller@14e03000mediatek,mt8195-wpesys_vpp10larb@14e04000mediatek,mt8195-smi-larb@i apbsmi*~larb@14e05000mediatek,mt8195-smi-larbPY  apbsmigals*_syscon@14f00000mediatek,mt8195-vppsys1syscon9V mutex@14f01000mediatek,mt8195-vpp-mutex[{9V '*larb@14f02000mediatek,mt8195-smi-larb i  apbsmigals*}larb@14f03000mediatek,mt8195-smi-larb0Z  apbsmigals*^display@14f06000mediatek,mt8195-mdp3-split`9V `+,*display@14f07000mediatek,mt8195-mdp3-tccp9V pdma-controller@14f08000mediatek,mt8195-mdp3-rdma9V Qrj*ydma-controller@14f09000mediatek,mt8195-mdp3-rdma9V Q rj*ydma-controller@14f0a000mediatek,mt8195-mdp3-rdma9V Q rX*ydisplay@14f0b000mediatek,mt8195-mdp3-fg9V  display@14f0c000mediatek,mt8195-mdp3-fg9V  display@14f0d000mediatek,mt8195-mdp3-fg9V  display@14f0e000mediatek,mt8195-mdp3-hdr9V display@14f0f000mediatek,mt8195-mdp3-hdr9V display@14f10000mediatek,mt8195-mdp3-hdr9V  display@14f11000mediatek,mt8195-mdp3-aal[i9V *display@14f12000mediatek,mt8195-mdp3-aal [j9V *display@14f13000mediatek,mt8195-mdp3-aal0[k9V 0!*display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz@9V @Qdisplay@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszP9V PQ$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz`9V `Q%display@14f17000mediatek,mt8195-mdp3-tdshpp9V pdisplay@14f18000mediatek,mt8195-mdp3-tdshp9V (display@14f19000mediatek,mt8195-mdp3-tdshp9V )display@14f1a000mediatek,mt8195-mdp3-merge9V *display@14f1b000mediatek,mt8195-mdp3-merge9V *display@14f1c000mediatek,mt8195-mdp3-color[t9V *display@14f1d000mediatek,mt8195-mdp3-color9V [u*display@14f1e000mediatek,mt8195-mdp3-color[v9V *display@14f1f000mediatek,mt8195-mdp3-ovl[w9V *rjdisplay@14f20000mediatek,mt8195-mdp3-padding9V *display@14f21000mediatek,mt8195-mdp3-padding9V *display@14f22000mediatek,mt8195-mdp3-padding 9V *dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot09V 0Qrj*ydma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot@9V @Qrj*ydma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotP9V PQrX*yclock-controller@15000000mediatek,mt8195-imgsys$larb@15001000mediatek,mt8195-smi-larb k$$$   apbsmigals*smi@15002000mediatek,mt8195-smi-sub-common $$ apbsmigals0Y*nsmi@15003000mediatek,mt8195-smi-sub-common0$$$  apbsmigals0i*kclock-controller@15110000 mediatek,mt8195-imgsys1_dip_topllarb@15120000mediatek,mt8195-smi-larb k$l apbsmi*clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"mlarb@15230000mediatek,mt8195-smi-larb# k$m apbsmi*clock-controller@15330000mediatek,mt8195-ipesys3%larb@15340000mediatek,mt8195-smi-larb4 n%% apbsmi*`clock-controller@16000000mediatek,mt8195-camsys&larb@16001000mediatek,mt8195-smi-larb o&&&  apbsmigals*larb@16002000mediatek,mt8195-smi-larb p&& apbsmi*asmi@16004000mediatek,mt8195-smi-sub-common@&&& apbsmigals0i*osmi@16005000mediatek,mt8195-smi-sub-commonP&& apbsmigals0Y*plarb@16012000mediatek,mt8195-smi-larb pqq apbsmi* blarb@16013000mediatek,mt8195-smi-larb0orr apbsmi* larb@16014000mediatek,mt8195-smi-larb@pss apbsmi*!hlarb@16015000mediatek,mt8195-smi-larbPott apbsmi*!clock-controller@1604f000mediatek,mt8195-camsys_rawaqclock-controller@1606f000mediatek,mt8195-camsys_yuvarclock-controller@1608f000mediatek,mt8195-camsys_rawbsclock-controller@160af000mediatek,mt8195-camsys_yuvb tclock-controller@16140000mediatek,mt8195-camsys_mrawularb@16141000mediatek,mt8195-smi-larbo&u&  apbsmigals*"larb@16142000mediatek,mt8195-smi-larb puu apbsmi*"gclock-controller@17200000mediatek,mt8195-ccusys vlarb@17201000mediatek,mt8195-smi-larb pvv apbsmi*cvideo-codec@18000000mediatek,mt8195-vcodec-deceWrj+ @`video-codec@2000mediatek,mtk-vcodec-lat-soc rXX A   selvdeclattopBAR*video-codec@10000mediatek,mtk-vcodec-lat[0rjjjjjj A   selvdeclattopBAR*video-codec@25000mediatek,mtk-vcodec-coreP[Prjjjjjjjjjj A selvdeclattopBAR*larb@1800d000mediatek,mt8195-smi-larbi  apbsmi*larb@1800e000mediatek,mt8195-smi-larbw  apbsmi*fclock-controller@1800f000mediatek,mt8195-vdecsys_soc larb@1802e000mediatek,mt8195-smi-larbi apbsmi*clock-controller@1802f000mediatek,mt8195-vdecsyslarb@1803e000mediatek,mt8195-smi-larbw! apbsmi*eclock-controller@1803f000mediatek,mt8195-vdecsys_core1!clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsys"larb@1a010000mediatek,mt8195-smi-larbi"" apbsmi*video-codec@1a020000mediatek,mt8195-vcodec-encHrj`jajbjcjdjvjwjxjy[UeW"  venc_selB@R*+jpgdec-mastermediatek,mt8195-jpgdec*0rjmjnjrjsjtju+jpgdec@1a040000mediatek,mt8195-jpgdec-hw0rjmjnjrjsjtju[W" jpgdec*jpgdec@1a050000mediatek,mt8195-jpgdec-hw0rjmjnjrjsjtju[X" jpgdec*jpgdec@1b040000mediatek,mt8195-jpgdec-hw0rXXXXXX[\ jpgdec*clock-controller@1b000000mediatek,mt8195-vencsys_core1syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon x9xjpgenc-mastermediatek,mt8195-jpgenc* rXXXX+jpgenc@1a030000mediatek,mt8195-jpgenc-hw rjgjhjijl[V" jpgenc*jpgenc@1b030000mediatek,mt8195-jpgenc-hw rXXXX[[ jpgenc*larb@1b010000mediatek,mt8195-smi-larbY   apbsmigals*dovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl[|*rj9xrdma@1c002000mediatek,mt8195-disp-rdma [~*rj9x color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0[*9x0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@[*9x@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalP[*9xPgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`[*9x`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherp[* 9xpdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi[**y enginedigitalhsgydphy kdisableddsc@1c009000mediatek,mt8195-disp-dsc[*9xdsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi [*+z enginedigitalhsgzdphy kdisabledmerge@1c014000mediatek,mt8195-disp-merge@[*9x@dp-intf@1c015000mediatek,mt8195-dp-intfP[, pixelenginepll kdisabledmutex@1c016000mediatek,mt8195-disp-mutex`[*9x`QUlarb@1c018000mediatek,mt8195-smi-larbi((   apbsmigals*{larb@1c019000mediatek,mt8195-smi-larbY(   apbsmigals*[syscon@1c100000mediatek,mt8195-vdosys1syscon x9xo#smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$ apbsmigals0gals1*iiommu@1c01f000mediatek,mt8195-iommu-vdo8{|}~[i' bclk*jmutex@1c101000mediatek,mt8195-disp-mutex |vdo1_mutex[*#  vdo1_mutex9xQlarb@1c102000mediatek,mt8195-smi-larb i###  apbsmigals*|larb@1c103000mediatek,mt8195-smi-larb0Y##   apbsmigals*\dma-controller@1c104000mediatek,mt8195-vdo1-rdma@[#*rj@9x@ydma-controller@1c105000mediatek,mt8195-vdo1-rdmaP[#*rX`9xPydma-controller@1c106000mediatek,mt8195-vdo1-rdma`[#*rjA9x`ydma-controller@1c107000mediatek,mt8195-vdo1-rdmap[#*rXa9xpydma-controller@1c108000mediatek,mt8195-vdo1-rdma[#*rjB9xydma-controller@1c109000mediatek,mt8195-vdo1-rdma[#*rXb9xydma-controller@1c10a000mediatek,mt8195-vdo1-rdma[#*rjC9xydma-controller@1c10b000mediatek,mt8195-vdo1-rdma[#*rXc9xyvpp-merge@1c10c000mediatek,mt8195-disp-merge[# # mergemerge_async*9x#vpp-merge@1c10d000mediatek,mt8195-disp-merge[# # mergemerge_async*9x#vpp-merge@1c10e000mediatek,mt8195-disp-merge[# # mergemerge_async*9x#vpp-merge@1c10f000mediatek,mt8195-disp-merge[# # mergemerge_async*9x#vpp-merge@1c110000mediatek,mt8195-disp-merge[# # mergemerge_async*9x#dp-intf@1c113000mediatek,mt8195-dp-intf0[*#/# pixelenginepll kdisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp4|mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp9x@xPxpxxxxh#%# ###!#$#"#1#&#'#(#)#* mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top*rXdXe[(#3#4#5#6#7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-txPdp_calibration_data*[ kdisableddp-tx@1c600000mediatek,mt8195-dp-tx`dp_calibration_data*[ kdisabledthermal-zonescpu0-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= cpu1-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= cpu2-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= cpu3-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= cpu4-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= cpu5-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= cpu6-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= cpu7-thermaltripstrip-alert!L-passivetrip-crit!- criticalcooling-mapsmap080= vpu0-thermaltripstrip-alert!L-passivetrip-crit!- criticalvpu1-thermal tripstrip-alert!L-passivetrip-crit!- criticalgpu-thermal tripstrip-alert!L-passivetrip-crit!- criticalgpu1-thermal tripstrip-alert!L-passivetrip-crit!- criticalvdec-thermal tripstrip-alert!L-passivetrip-crit!- criticalimg-thermal tripstrip-alert!L-passivetrip-crit!- criticalinfra-thermaltripstrip-alert!L-passivetrip-crit!- criticalcam0-thermaltripstrip-alert!L-passivetrip-crit!- criticalcam1-thermaltripstrip-alert!L-passivetrip-crit!- criticalchosenLserial0:921600n8memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-updrive-strengthdrive-strength-microampbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupusb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-max-frequencybits#phy-cellsoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-path