"8H( -xunlong,orangepi-r1-plus-ltsrockchip,rk3328 +7Xunlong Orange Pi R1 Plus LTSaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/usb@ff600000/device@2/mmc@ff500000cpus+cpu@0cpuarm,cortex-a53xpsci @+8E@Wdu cpu@1cpuarm,cortex-a53xpsci @+8E@Wdu cpu@2cpuarm,cortex-a53xpsci @+8E@Wdu cpu@3cpuarm,cortex-a53xpsci @+8E@Wdu idle-statespscicpu-sleeparm,idle-statexl2-cachecache@-opp-table-0operating-points-v2 opp-408000000Q~)@:opp-600000000#F~)@opp-8160000000,B@)@opp-1008000000<)@opp-1200000000G()@opp-1296000000M?d )@analog-soundsimple-audio-cardFi2s_yAnalog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem  disabledhdmi-soundsimple-audio-cardFi2s_yHDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mCi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk tx!default/ disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrx!defaultsleep/9 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd8io-domains"rockchip,rk3328-io-voltage-domainokayCP^lzgpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+:power-domain@6power-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrx!default /  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrx!default /!"# disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrx!default/$okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk!default/% disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk!default/&okaypmic@18rockchip,rk805 'xin32krk805-clkout2/(!default(IW)c)o){))regulatorsDCDC_REG1vdd_log 4 0regulator-state-mem1B@DCDC_REG2vdd_arm 4 0regulator-state-mem1~DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vcc_io2Z2Zregulator-state-mem12ZLDO_REG1vcc_18w@w@regulator-state-mem1w@LDO_REG2 vcc18_emmcw@w@regulator-state-mem1w@LDO_REG3vdd_10B@B@regulator-state-mem1B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk!default/* disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk!default/+ disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrx!default/,-./okayflash@0jedec,spi-norMwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk!default/0_ disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk!default/1_ disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclk!default/2_okaypwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk!default/3_ disableddma-controller@ff1f0000arm,pl330arm,primecell@j apb_pclkthermal-zonessoc-thermal4tripstrip-point0ppassivetrip-point1Lpassive5soc-crits criticalcooling-mapsmap050 tsadc@ff250000rockchip,rk3328-tsadc% : $P$tsadcapb_pclk!initdefaultsleep/697/69B @tsadc-apbL8Ypokay4efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aDadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclk9V @saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore9fiommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk9:iommu@ff350800rockchip,iommu5@  F aclkiface:9video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccore AB ׄׄ;:iommu@ff360480rockchip,iommu 6@6@ JB aclkiface:;vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop9 @axiahbdclk< disabledport+ endpoint@0=Biommu@ff373f00rockchip,iommu7?  ; aclkiface disabled<hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #Fiahbisfrcec%>*hdmi!default /?@AL8 disabledports+port@0endpointB=port@1codec@ff410000rockchip,rk3328-codecA* pclkmclkL8 disabledphy@ff430000rockchip,rk3328-hdmi-phyC SCysysclkrefoclkrefpclk hdmi_phy4D @cpu-versionQ disabled>clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconDL8\ x=&'(ABDC"\5H4$izCCC|n6n6n6ׄn6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyCphyclk usb480m_phy {iEokayEotg-portQ$;<=otg-bvalidotg-idlinestateokayRhost-portQ > linestateokaySmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleQр9m@resetokay/FGHI!defaultJmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleQр9n@reset disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleQр9o@reset disabledethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac9c @stmmacethL8okay dfiKKinputLrgmii/M!default"mdiosnps,dwmac-mdio+ethernet-phy@0ethernet-phy-ieee802.3-c22+IsY@h/N!default:P 'Lethernet@ff550000rockchip,rk3328-gmacUL8 macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy9b @stmmacethrmiiOoutput disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V9d!default/PQOusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motg host   )@ %R *usb2-phyokayusb@ff5c0000 generic-ehci\  NE%S*usbokayusb@ff5d0000 generic-ohci]  NE%S*usbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-sampleQр9h@reset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clk host 8utmi_wide A b z   okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400  @ @ `   crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclk9D @crypto-rstpinctrlrockchip,rk3328-pinctrlL8+ gpio@ff210000rockchip,gpio-bank! 3  dgpio@ff220000rockchip,gpio-bank" 4  'gpio@ff230000rockchip,gpio-bank# 5  bgpio@ff240000rockchip,gpio-bank$ 6  cpcfg-pull-up Vpcfg-pull-down )^pcfg-pull-none 8Tpcfg-pull-none-2ma 8 E]pcfg-pull-up-2ma  Epcfg-pull-up-4ma  EWpcfg-pull-none-4ma 8 EZpcfg-pull-down-4ma ) Epcfg-pull-none-8ma 8 EXpcfg-pull-up-8ma  EYpcfg-pull-none-12ma 8 E [pcfg-pull-up-12ma  E \pcfg-output-high Tpcfg-output-low `pcfg-input-high  kUpcfg-input ki2c0i2c0-xfer xTT%i2c1i2c1-xfer xTT&i2c2i2c2-xfer x TT*i2c3i2c3-xfer xTT+i2c3-pins xTThdmi_i2chdmii2c-xfer xTT@pdm-0pdmm0-clk xTpdmm0-fsync xTpdmm0-sdi0 xTpdmm0-sdi1 xTpdmm0-sdi2 xTpdmm0-sdi3 xTpdmm0-clk-sleep xUpdmm0-sdi0-sleep xUpdmm0-sdi1-sleep xUpdmm0-sdi2-sleep xUpdmm0-sdi3-sleep xUpdmm0-fsync-sleep xUtsadcotp-pin x T6otp-out x T7uart0uart0-xfer x TVuart0-cts x Tuart0-rts x T uart0-rts-pin x Tuart1uart1-xfer xTV!uart1-cts xT"uart1-rts xT#uart1-rts-pin xTuart2-0uart2m0-xfer xTVuart2-1uart2m1-xfer xTV$spi0-0spi0m0-clk xVspi0m0-cs0 x Vspi0m0-tx x Vspi0m0-rx x Vspi0m0-cs1 x Vspi0-1spi0m1-clk xVspi0m1-cs0 xVspi0m1-tx xVspi0m1-rx xVspi0m1-cs1 xVspi0-2spi0m2-clk xV,spi0m2-cs0 xV/spi0m2-tx xV-spi0m2-rx xV.i2s1i2s1-mclk xTi2s1-sclk xTi2s1-lrckrx xTi2s1-lrcktx xTi2s1-sdi xTi2s1-sdo xTi2s1-sdio1 xTi2s1-sdio2 xTi2s1-sdio3 xTi2s1-sleep xUUUUUUUUUi2s2-0i2s2m0-mclk xTi2s2m0-sclk xTi2s2m0-lrckrx xTi2s2m0-lrcktx xTi2s2m0-sdi xTi2s2m0-sdo xTi2s2m0-sleep` xUUUUUUi2s2-1i2s2m1-mclk xTi2s2m1-sclk xTi2sm1-lrckrx xTi2s2m1-lrcktx xTi2s2m1-sdi xTi2s2m1-sdo xTi2s2m1-sleepP xUUUUUspdif-0spdifm0-tx xTspdif-1spdifm1-tx xTspdif-2spdifm2-tx xTsdmmc0-0sdmmc0m0-pwren xWsdmmc0m0-pin xWsdmmc0-1sdmmc0m1-pwren xWsdmmc0m1-pin xWesdmmc0sdmmc0-clk xXFsdmmc0-cmd xYGsdmmc0-dectn xWHsdmmc0-wrprt xWsdmmc0-bus1 xYsdmmc0-bus4@ xYYYYIsdmmc0-pins xWWWWWWWWsdmmc0extsdmmc0ext-clk xZsdmmc0ext-cmd xWsdmmc0ext-wrprt xWsdmmc0ext-dectn xWsdmmc0ext-bus1 xWsdmmc0ext-bus4@ xWWWWsdmmc0ext-pins xWWWWWWWWsdmmc1sdmmc1-clk x Xsdmmc1-cmd x Ysdmmc1-pwren xYsdmmc1-wrprt xYsdmmc1-dectn xYsdmmc1-bus1 xYsdmmc1-bus4@ xYYYYsdmmc1-pins x W WWWWWWWWemmcemmc-clk x[emmc-cmd x\emmc-pwren xTemmc-rstnout xTemmc-bus1 x\emmc-bus4@ x\\\\emmc-bus8 x\\\\\\\\pwm0pwm0-pin xT0pwm1pwm1-pin xT1pwm2pwm2-pin xT2pwmirpwmir-pin xT3gmac-1rgmiim1-pins` x X ZZXZZZ Z ZX XZZXXX XZXXXXMrmiim1-pins x][]]]] ] ][ [ T TTTTTgmac2phyfephyled-speed10 xTfephyled-duplex xTfephyled-rxm1 xTPfephyled-txm1 xTfephyled-linkm1 xTQtsadc_pintsadc-int x Ttsadc-pin x Thdmi_pinhdmi-cec xT?hdmi-hpd x^Acif-0dvp-d2d9-m0 xTTTTT T T TTTTTcif-1dvp-d2d9-m1 xTTTTTTTTTTTTgmac2ioeth-phy-reset-pin x^Nledslan-led-pin xT_sys-led-pin xT`wan-led-pin xTalanlan-vdd-pin xTfpmicpmic-int-l xV(chosen serial2:1500000n8gmac-clock fixed-clocksY@ gmac_clkinKleds gpio-leds /_`a!defaultled-0 lan  bled-1 status  c heartbeatled-2 wan  bsdmmc-regulatorregulator-fixed d/e!defaultvcc_sd Jvcc-sys-regulatorregulator-fixedvcc_sysLK@LK@)vdd-5v-lan-regulatorregulator-fixed  b/f!default vdd_5v_lan ) compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-sd-highspeeddisable-wpvmmc-supplytx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-handlephy-modephy-supplysnps,aalrx_delaytx_delaymotorcomm,auto-sleep-disabledmotorcomm,clk-out-frequency-hzmotorcomm,keep-pll-enabledmotorcomm,rx-clk-drv-microampmotorcomm,rx-data-drv-microampreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathfunctioncolorlinux,default-triggergpiovin-supplyenable-active-high