U 8H( HH.radxa,nio-12lmediatek,mt8395mediatek,mt8195 +7Radxa NIO 12L =embeddedaliasesJ/soc/dp-intf@1c015000S/soc/dp-intf@1c113000\/soc/mailbox@10320000a/soc/mailbox@10330000f/soc/hdr-engine@1c114000m/soc/mutex@1c016000t/soc/mutex@1c101000{/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e02000/soc/i2c@11e03000/soc/i2c@11e04000/soc/i2c@11e00000 /soc/i2c@11e01000/soc/ethernet@11021000/soc/serial@11001100!/soc/serial@11001200)/soc/spi@11010000./soc/spi@11012000cpus+cpu@03cpuarm,cortex-a55?CpsciQeec3@u4@@ cpu@1003cpuarm,cortex-a55?CpsciQeec3@u4@@ cpu@2003cpuarm,cortex-a55?CpsciQeec3@u4@@ cpu@3003cpuarm,cortex-a55?CpsciQeec3@u4@@cpu@4003cpuarm,cortex-a78?CpsciQefu@@  cpu@5003cpuarm,cortex-a78?CpsciQefu@@  cpu@6003cpuarm,cortex-a78?CpsciQefu@@  cpu@7003cpuarm,cortex-a78?CpsciQefu@@  cpu-mapcluster0core0# core1# core2# core3#core4#core5#core6#core7#idle-states'pscicpu-retention-larm,idle-state4K\2m_}Dcpu-retention-barm,idle-state4K\-m}cpu-off-larm,idle-state4K\7m}Hcpu-off-barm,idle-state4K\2m}l2-cache0cache@l2-cache1cache@ l3-cachecache @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-sound disabledfixed-factor-clock-13mfixed-factor-clock clk13m,oscillator-26m fixed-clockeclk26moscillator-32k fixed-clockeclk32kperformance-controller@11bc10mediatek,cpufreq-hw ? 0 *opp-table-gpuoperating-points-v2Duopp-390000000O>V hopp-410000000OpV opp-431000000OV opp-473000000O1h@V <opp-515000000OFV <opp-556000000O!#V Ҧopp-598000000O#V opp-640000000O&%V opp-670000000O'cV opp-700000000O)'V Lopp-730000000O+V }opp-760000000O-LV `opp-790000000O/qV 4opp-820000000O05V opp-850000000O2V @opp-880000000O4sV qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0Jsmctimerarm,armv8-timer @   soc+ simple-busdkinterrupt-controller@c000000 arm,gic-v3v  ?    ppi-partitionsinterrupt-partition-0 interrupt-partition-1syscon@10000000 mediatek,mt8195-topckgensyscon?syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd?syscon@10003000mediatek,mt8195-pericfgsyscon?0Bpinctrl@10005000mediatek,mt8195-pinctrl?PBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintveth-default-pins>pins-ccUVWX&pins-mdioYZ5pins-power[\Bpins-rst]pins-rxdQRSTpins-txdMNOP&eth-sleep-pins?pins-ccUVWXpins-mdioYZN[pins-rxdQRSTpins-txdMNOPi2c2-pinscpins-bus  i&vi2c4-pinsfpins-busivi2c6-pins\pinsNmmc0-default-pinsGpins-clkzf&pins-cmd-dat$~}|{wvutyie&5pins-rstxie&mmc0-uhs-pinsHpins-clkzf&pins-cmd-dat$~}|{wvutyie&5pins-dsf&pins-rstxie&mmc1-default-pinsKpins-clkof&pins-cmd-datnpqrsie&5mmc1-detect-pinsLpins-insertimt6360-pins]pins-irqde5ipcie0-default-pinsWpins-bus ipcie1-default-pinsZpins-bus Nspi1-default-pins8pins-busNspi2-default-pins9pins-busNuart0-pins3pins-busbcuart1-pins4pins-busfgusb3p0-default-pinsCpins-vbus?5usb2p0-default-pinsRpins-iddig5ipins-vbuswifi-vreg-pinspins-wifi-pmu-enABpins-wifi-vreg-enCsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd?`power-controller!mediatek,mt8195-power-controller+/power-domain@8?+power-domain@9? mfgalt+power-domain@10? power-domain@11? power-domain@12? power-domain@13? power-domain@14?power-domain@15? @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@24?vdec1-0power-domain@27?  venc1-larbpower-domain@16?8!$!%!&!'!(!)Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17?""vppsys1vppsys1-0vppsys1-1power-domain@22? ####$wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23?$vdec0-0power-domain@25?%vdec2-0power-domain@26?& venc0-larbpower-domain@18? '''&vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19?power-domain@20?power-domain@21?Qhdmi_txpower-domain@28?((  img-0img-1+power-domain@29?power-domain@30?()ipeipe-0ipe-1power-domain@31?(*****cam-0cam-1cam-2cam-3cam-4+power-domain@32? power-domain@33?!power-domain@34?"power-domain@0?power-domain@1?power-domain@2?power-domain@3?power-domain@4?57csi_rx_topcsi_rx_top1power-domain@5?+ etherpower-domain@6?Xn adspadsp1+power-domain@7? g"n2audioaudio1audio2audio3watchdog@10007000mediatek,mt8195-wdt?p2syscon@1000c000"mediatek,mt8195-apmixedsyssyscon?timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer?p ,pwrap@10024000mediatek,mt8195-pwrapsyscon?@pwrap spiwrap$pmicmediatek,mt6359v 'adcmediatek,mt6359-auxadc;mt6359codecregulatorsbuck_vs1Mvs1\ 5t!buck_vgpu11Mvgpu11\t7 buck_vmodemMvmodem\t*buck_vpuMvpu\t7 buck_vcoreMvcore\t  buck_vs2Mvs2\ 5tjbuck_vpaMvpa\ t7,buck_vproc2Mvproc2\t7L buck_vproc1Mvproc1\t7L buck_vcore_sshub Mvcore_sshub\t7buck_vgpu11_sshub Mvgpu11_sshub\t7ldo_vaud18Mvaud18\w@tw@ldo_vsim1Mvsim1\t/M`ldo_vibrMvibr\Ot2Zdldo_vrf12Mvrf12\t ldo_vusbMvusb\-t-Dldo_vsram_proc2 Mvsram_proc2\ tLldo_vio18Mvio18\tldo_vcamioMvcamio\tldo_vcn18Mvcn18\w@tw@ldo_vfe28Mvfe28\*t*xldo_vcn13Mvcn13\ t ldo_vcn33_1_bt Mvcn33_1_bt\*t5gldo_vcn33_1_wifi Mvcn33_1_wifi\*t5gldo_vaux18Mvaux18\w@tw@ldo_vsram_others Mvsram_others\ qt qldo_vefuseMvefuse\tldo_vxo22Mvxo22\w@t!ldo_vrfckMvrfck\`tldo_vrfck_1Mvrfck\tjldo_vbif28Mvbif28\*t*ldo_vio28Mvio28\*t2Zldo_vemcMvemc\,@ t2Zldo_vemc_1Mvemc\&%t2ZIldo_vcn33_2_bt Mvcn33_2_bt\2Zt2Zldo_vcn33_2_wifi Mvcn33_2_wifi\*t5gldo_va12Mva12\Ot ldo_va09Mva09\ 5tOldo_vrf18Mvrf18\tPldo_vsram_md Mvsram_md\ t*ldo_vufsMvufs\tJldo_vm18Mvm18\tldo_vbbckMvbbck\tOldo_vsram_proc1 Mvsram_proc1\ tLldo_vsim2Mvsim2\t/M`ldo_vsram_others_sshubMvsram_others_sshub\ tmt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi ?p pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+pmic@6mediatek,mt6315-regulator?regulatorsvbuck1vbuck1MVbcpu\t7  pmic@7mediatek,mt6315-regulator?regulatorsvbuck1vbuck1MVgpu\t7 infra-iommu@10315000mediatek,mt8195-iommu-infra?1PPPTmailbox@10320000mediatek,mt8195-gce?2@ mailbox@10330000mediatek,mt8195-gce?3@ vscp@10500000mediatek,mt8195-scp0?Prpsramcfgl1tcmokay-wclock-controller@10720000mediatek,mt8195-scp_adsp?r.dsp@10803000mediatek,mt8195-dsp ?0 cfgsram,Xn.#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h%/3rxtx>01 disabledmailbox@10816000mediatek,mt8195-adsp-mbox ?`0mailbox@10817000mediatek,mt8195-adsp-mbox ?p1mt8195-afe-pcm@10890000mediatek,mt8195-audio?E%/6W2 ^audiosysg"#neabcd2.clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbusokayj3tdefaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbusokayj4tdefaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart?  baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc? main; disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon?0+spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+?parent-clksel-clkspi-clk disabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap? W56$lvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svs?main75(svs-calibration-datat-calibration-dataW^svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm?%/*0mainmm disabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm?+Nmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+?3parent-clksel-clkspi-clkokayj8tdefaultspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+? 4parent-clksel-clkspi-clkokayj9tdefaultspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+?05parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+?<parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+?=parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave?Rspi disabledspi@1101e000mediatek,mt8195-spi-slave?Sspi disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a?@macirq.axiapbmac_mainptp_refrmii_internalmac_cg0++RST+ RST%/:;<+6Aokay Nrgmii-rxidW=tdefaultsleepj>b?l ] N mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916?=stmmac-axi-config:rx-queues-config;queue0queue1queue2queue3tx-queues-config3I<queue0[gqueue1[gqueue2[gqueue3[gusb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 ? - > macippcd ?+/Bsys_ckref_ckmcu_cku@Az BgokaytdefaultjChostDusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci?mac,-$/B$sys_ckref_ckmcu_ckdma_ckxhci_ckokayEportendpointF`mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc ?#sourcehclksource_cgokaytdefaultstate_uhsjGbH  L  + < K Z b h vI Jmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc ?$$sourcehclksource_cgokaytdefaultstate_uhsjKLbK     Z   vM Nmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc ?% Isourcehclksource_cg  disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu?'W56$lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ?))> macippcuO./$++$sys_ckref_ckmcu_ckdma_ckxhci_ck Bhzokay DP usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 ?*-*> macippcd*?+0++sys_ckref_ckmcu_ckuQz BiokaytdefaultjRDusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci?mac1+sys_ckokayPusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 ?+-+> macippcd+?+2++ sys_ckref_ckmcu_ckuSz Bj disabledusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci?mac3+ sys_ck disabledpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcie3pci+?/@ pcie-mac 8d  T 0V#&+K+/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memGuU pcie-phy%/W^macv ` 1VVVVokaytdefaultjWinterrupt-controllervVpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcie3pci+?/@ pcie-mac 8d$$ $ $  T (WXQ+/pl_250mtl_26mtl_96mtl_32kperi_26mperi_memHuX pcie-phy%/W^macv ` 1YYYYokaytdefaultjZinterrupt-controllervYspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor?29o++ spisfaxi+ disabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse?+usb3-tx-imp@184,1? ?lusb3-rx-imp@184,2? ?kusb3-intr@185? ?jusb3-tx-imp@186,1? ?iusb3-rx-imp@186,2? ?husb3-intr@187? ?gusb2-intr-p0@188,1? ?usb2-intr-p1@188,2? ?usb2-intr-p2@189,1? ?usb2-intr-p3@189,2? ?pciephy-rx-ln1@190,1? ?spciephy-tx-ln1-nmos@190,2? ?rpciephy-tx-ln1-pmos@191,1? ?qpciephy-rx-ln0@191,2? ?ppciephy-tx-ln0-nmos@192,1? ?opciephy-tx-ln0-pmos@192,2? ?npciephy-glb-intr@193? ?mdp-data@1ac?lvts1-calib@1bc?5lvts2-calib@1d0?86svs-calib@580?d7socinfo-data1@7a0?t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+dokayusb-phy@0?ref DQt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+d disabledusb-phy@0?ref DSdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx? mipi_tx0_pll D disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx? mipi_tx1_pll D disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"[; maindma+ disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"[; maindma+okayej\tdefaultpmic@34mediatek,mt6360?4 'eIRQBvj]chargermediatek,mt6360-chg O@usb-otg-vbus-regulator Musb-otg-vbus\C(tXEregulatormediatek,mt6360-regulator h^ x_buck1 Memi_vdd2\t  buck2 Memi_vddq\t  _ldo1 Mext_lcd_3v3\2Zt2Zldo2 Mpanel1_p1v8\w@tw@ldo3Mvmc_pmu\Ot6Nldo5 Mvmch_pmu\2Zt2ZMldo6 Mmt6360_ldo6\ t ldo7 Memi_vmddr_en\ t typecmediatek,mt6360-tcpc 'dPD_IRQBconnectorusb-c-connector USB-C dual  dual sink "d ",ports+port@0?endpoint`Fport@2?endpointaei2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ? "[; maindma+ disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s?0[i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"b; maindma+ disabledi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?"b; maindma+ disabledi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ? "b; maindma+okayejctdefaulttypec-mux@48 ite,it5205?H   dportendpointeai2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?0"b; maindma+ disabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c ?@"b; maindma+okayejftdefaultclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w?Pbt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+d%/okayusb-phy@0?  refda_ref DOusb-phy@700? refda_ref ghiintrrx_imptx_imp DXt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+dokayusb-phy@0?  refda_ref D@usb-phy@700? refda_ref jklintrrx_imptx_imp DAphy@11e80000mediatek,mt8195-pcie-phy?sifmnopqrsGglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1%/ DokayUufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy? unipromp D disabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm?@t0 jobmmugpu u(%/ / / / / core0core1core2core3core4okay +clock-controller@13fbf000mediatek,mt8195-mfgcfg?tsyscon@14000000mediatek,mt8195-vppsys0syscon? 7vdma-controller@14001000mediatek,mt8195-mdp3-rdma? 7v O  cw%/ px<>v v vvv wdisplay@14002000mediatek,mt8195-mdp3-fg?  7v display@14003000mediatek,mt8195-mdp3-stitch?0 7v0display@14004000mediatek,mt8195-mdp3-hdr?@ 7v@"display@14005000mediatek,mt8195-mdp3-aal?PF 7vP %/display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?` 7v` O% display@14007000mediatek,mt8195-mdp3-tdshp?p 7vp#display@14008000mediatek,mt8195-mdp3-color?I 7v$%/display@14009000mediatek,mt8195-mdp3-ovl?J 7v%%/ pxdisplay@1400a000mediatek,mt8195-mdp3-padding? 7v%/display@1400b000mediatek,mt8195-mdp3-tcc? 7vdma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot? 7v O + px%/ wmutex@1400f000mediatek,mt8195-vpp-mutex?P 7v%/smi@14010000mediatek,mt8195-smi-sub-common?apbsmigals0 y%/zsmi@14011000mediatek,mt8195-smi-sub-common?apbsmigals0 y%/smi@14012000mediatek,mt8195-smi-common-vpp?  apbsmigals0gals1%/ylarb@14013000mediatek,mt8195-smi-larb?0  zapbsmi%/}iommu@14018000mediatek,mt8195-iommu-vpp?8 {|}~Rbclk%/xclock-controller@14e00000mediatek,mt8195-wpesys?#clock-controller@14e02000mediatek,mt8195-wpesys_vpp0? clock-controller@14e03000mediatek,mt8195-wpesys_vpp1?0larb@14e04000mediatek,mt8195-smi-larb?@  ##apbsmi%/larb@14e05000mediatek,mt8195-smi-larb?P  y## apbsmigals%/syscon@14f00000mediatek,mt8195-vppsys1syscon? 7v "mutex@14f01000mediatek,mt8195-vpp-mutex?{ 7v "'%/larb@14f02000mediatek,mt8195-smi-larb?   "" apbsmigals%/larb@14f03000mediatek,mt8195-smi-larb?0  z"" apbsmigals%/~display@14f06000mediatek,mt8195-mdp3-split?` 7v `""+",%/display@14f07000mediatek,mt8195-mdp3-tcc?p 7v p"dma-controller@14f08000mediatek,mt8195-mdp3-rdma? 7v  O" p%/ wdma-controller@14f09000mediatek,mt8195-mdp3-rdma? 7v  O"  p%/ wdma-controller@14f0a000mediatek,mt8195-mdp3-rdma? 7v  O"  px%/ wdisplay@14f0b000mediatek,mt8195-mdp3-fg? 7v " display@14f0c000mediatek,mt8195-mdp3-fg? 7v " display@14f0d000mediatek,mt8195-mdp3-fg? 7v " display@14f0e000mediatek,mt8195-mdp3-hdr? 7v "display@14f0f000mediatek,mt8195-mdp3-hdr? 7v "display@14f10000mediatek,mt8195-mdp3-hdr? 7v " display@14f11000mediatek,mt8195-mdp3-aal?i 7v "%/display@14f12000mediatek,mt8195-mdp3-aal? j 7v "%/display@14f13000mediatek,mt8195-mdp3-aal?0k 7v 0"!%/display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?@ 7v @ O"display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?P 7v P O"$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz?` 7v ` O"%display@14f17000mediatek,mt8195-mdp3-tdshp?p 7v p"display@14f18000mediatek,mt8195-mdp3-tdshp? 7v "(display@14f19000mediatek,mt8195-mdp3-tdshp? 7v ")display@14f1a000mediatek,mt8195-mdp3-merge? 7v "%/display@14f1b000mediatek,mt8195-mdp3-merge? 7v "%/display@14f1c000mediatek,mt8195-mdp3-color?t 7v "%/display@14f1d000mediatek,mt8195-mdp3-color? 7v u"%/display@14f1e000mediatek,mt8195-mdp3-color?v 7v "%/display@14f1f000mediatek,mt8195-mdp3-ovl?w 7v "%/ pdisplay@14f20000mediatek,mt8195-mdp3-padding? 7v "%/display@14f21000mediatek,mt8195-mdp3-padding? 7v "%/display@14f22000mediatek,mt8195-mdp3-padding?  7v "%/dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot?0 7v 0 O" p%/ wdma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot?@ 7v @ O" p%/ wdma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot?P 7v P O" px%/ wclock-controller@15000000mediatek,mt8195-imgsys?(larb@15001000mediatek,mt8195-smi-larb?  (((  apbsmigals%/smi@15002000mediatek,mt8195-smi-sub-common? ((apbsmigals0 y%/smi@15003000mediatek,mt8195-smi-sub-common?0((( apbsmigals0 %/clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top?larb@15120000mediatek,mt8195-smi-larb?  (apbsmi%/clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr?clock-controller@15220000mediatek,mt8195-imgsys1_wpe?"larb@15230000mediatek,mt8195-smi-larb?#  (apbsmi%/clock-controller@15330000mediatek,mt8195-ipesys?3)larb@15340000mediatek,mt8195-smi-larb?4  ))apbsmi%/clock-controller@16000000mediatek,mt8195-camsys?*larb@16001000mediatek,mt8195-smi-larb?  *** apbsmigals%/larb@16002000mediatek,mt8195-smi-larb?   **apbsmi%/smi@16004000mediatek,mt8195-smi-sub-common?@***apbsmigals0 %/smi@16005000mediatek,mt8195-smi-sub-common?P**apbsmigals0 y%/larb@16012000mediatek,mt8195-smi-larb?   apbsmi%/ larb@16013000mediatek,mt8195-smi-larb?0  apbsmi%/ larb@16014000mediatek,mt8195-smi-larb?@  apbsmi%/!larb@16015000mediatek,mt8195-smi-larb?P  apbsmi%/!clock-controller@1604f000mediatek,mt8195-camsys_rawa?clock-controller@1606f000mediatek,mt8195-camsys_yuva?clock-controller@1608f000mediatek,mt8195-camsys_rawb?clock-controller@160af000mediatek,mt8195-camsys_yuvb? clock-controller@16140000mediatek,mt8195-camsys_mraw?larb@16141000mediatek,mt8195-smi-larb?  ** apbsmigals%/"larb@16142000mediatek,mt8195-smi-larb?   apbsmi%/"clock-controller@17200000mediatek,mt8195-ccusys? larb@17201000mediatek,mt8195-smi-larb?   apbsmi%/video-codec@18000000mediatek,mt8195-vcodec-dec cw p+ ?@d`video-codec@2000mediatek,mtk-vcodec-lat-soc?  pxx A$$selvdeclattopA%/video-codec@10000mediatek,mtk-vcodec-lat?0 p A$$selvdeclattopA%/video-codec@25000mediatek,mtk-vcodec-core?PP p AselvdeclattopA%/larb@1800d000mediatek,mt8195-smi-larb?  $$apbsmi%/larb@1800e000mediatek,mt8195-smi-larb?  $apbsmi%/clock-controller@1800f000mediatek,mt8195-vdecsys_soc?$larb@1802e000mediatek,mt8195-smi-larb?  apbsmi%/clock-controller@1802f000mediatek,mt8195-vdecsys?larb@1803e000mediatek,mt8195-smi-larb?  %apbsmi%/clock-controller@1803f000mediatek,mt8195-vdecsys_core1?%clock-controller@190f3000mediatek,mt8195-apusys_pll?0clock-controller@1a000000mediatek,mt8195-vencsys?&larb@1a010000mediatek,mt8195-smi-larb?  &&apbsmi%/video-codec@1a020000mediatek,mt8195-vcodec-enc?H p`abcdvwxyU cw& venc_sel@%/+jpgdec-mastermediatek,mt8195-jpgdec%/0 pmnrstu+djpgdec@1a040000mediatek,mt8195-jpgdec-hw?0 pmnrstuW&jpgdec%/jpgdec@1a050000mediatek,mt8195-jpgdec-hw?0 pmnrstuX&jpgdec%/jpgdec@1b040000mediatek,mt8195-jpgdec-hw?0 pxxxxxx\ jpgdec%/clock-controller@1b000000mediatek,mt8195-vencsys_core1? syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon? > 7!jpgenc-mastermediatek,mt8195-jpgenc%/ pxxxx+djpgenc@1a030000mediatek,mt8195-jpgenc-hw? pghilV&jpgenc%/jpgenc@1b030000mediatek,mt8195-jpgenc-hw? pxxxx[ jpgenc%/larb@1b010000mediatek,mt8195-smi-larb?  y    apbsmigals%/ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl?|%/! p 7rdma@1c002000mediatek,mt8195-disp-rdma? ~%/! p 7 color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color?0%/! 70ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr?@%/! 7@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal?P%/! 7Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma?`%/! 7`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither?p%/!  7pdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi?%/!!*enginedigitalhsu dphy disableddsc@1c009000mediatek,mt8195-disp-dsc?%/! 7dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi? %/!!+enginedigitalhsu dphy disabledmerge@1c014000mediatek,mt8195-disp-merge?@%/! 7@dp-intf@1c015000mediatek,mt8195-dp-intf?P!,!pixelenginepll disabledmutex@1c016000mediatek,mt8195-disp-mutex?`%/! 7` OUlarb@1c018000mediatek,mt8195-smi-larb?  !(!(  apbsmigals%/larb@1c019000mediatek,mt8195-smi-larb?  y!(  apbsmigals%/{syscon@1c100000mediatek,mt8195-vdosys1syscon? > 7'smi@1c01b000mediatek,mt8195-smi-common-vdo? !%!&!)!$apbsmigals0gals1%/iommu@1c01f000mediatek,mt8195-iommu-vdo?8 !'bclk%/mutex@1c101000mediatek,mt8195-disp-mutex? vdo1_mutex%/' vdo1_mutex 7 Olarb@1c102000mediatek,mt8195-smi-larb?   ''' apbsmigals%/larb@1c103000mediatek,mt8195-smi-larb?0  y''  apbsmigals%/|dma-controller@1c104000mediatek,mt8195-vdo1-rdma?@'%/ p@ 7@ wdma-controller@1c105000mediatek,mt8195-vdo1-rdma?P'%/ px` 7P wdma-controller@1c106000mediatek,mt8195-vdo1-rdma?`'%/ pA 7` wdma-controller@1c107000mediatek,mt8195-vdo1-rdma?p'%/ pxa 7p wdma-controller@1c108000mediatek,mt8195-vdo1-rdma?'%/ pB 7 wdma-controller@1c109000mediatek,mt8195-vdo1-rdma?'%/ pxb 7 wdma-controller@1c10a000mediatek,mt8195-vdo1-rdma?'%/ pC 7 wdma-controller@1c10b000mediatek,mt8195-vdo1-rdma?'%/ pxc 7 wvpp-merge@1c10c000mediatek,mt8195-disp-merge?' 'mergemerge_async%/ 7 W'vpp-merge@1c10d000mediatek,mt8195-disp-merge?' 'mergemerge_async%/ 7 W'vpp-merge@1c10e000mediatek,mt8195-disp-merge?' 'mergemerge_async%/ 7 W'vpp-merge@1c10f000mediatek,mt8195-disp-merge?' 'mergemerge_async%/ 7 W'vpp-merge@1c110000mediatek,mt8195-disp-merge?' 'mergemerge_async%/ 7 W'dp-intf@1c113000mediatek,mt8195-dp-intf?0%/'/'pixelenginepll disabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp?@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp 7@Pph'%' '#'!'$'"'1'&'''(')'*mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top%/ pxdxe(W'3'4'5'6'7E^vdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-tx?Pdp_calibration_data%/  disableddp-tx@1c600000mediatek,mt8195-dp-tx?`dp_calibration_data%/  disabledthermal-zonescpu0-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ; cpu1-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ; cpu2-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ; cpu3-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ; cpu4-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ;cpu5-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ;cpu6-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ;cpu7-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcooling-mapsmap0 60 ;vpu0-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalvpu1-thermal    tripstrip-alert L +Epassivetrip-crit  + Ecriticalgpu-thermal    tripstrip-alert L +Epassivetrip-crit  + Ecriticalgpu1-thermal    tripstrip-alert L +Epassivetrip-crit  + Ecriticalvdec-thermal    tripstrip-alert L +Epassivetrip-crit  + Ecriticalimg-thermal    tripstrip-alert L +Epassivetrip-crit  + Ecriticalinfra-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcam0-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalcam1-thermal   tripstrip-alert L +Epassivetrip-crit  + Ecriticalchosen Jserial0:921600n8firmwareopteelinaro,optee-tzJsmcmemory@400000003memory?@regulator-wifi-3v3-enregulator-fixed Mwifi_3v3_en\2Zt2Z V Ctdefaultj iPregulator-vsysregulator-fixedMvsys t\LK@tLK@ iPregulator-vsys-buckregulator-fixed Mvsys_buck t\LK@tLK@ i^regulator-vcc5v0-sysregulator-fixed Mvcc5v0_sys treserved-memory+doptee@43200000?C  memory@50000000shared-dma-pool?P -memory@53000000shared-dma-pool?S@memory@54600000?T`  memory@60000000shared-dma-pool?` memory@62000000shared-dma-pool?b@ compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typedp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4ethernet0serial0serial1spi0spi1device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitpinmuxdrive-strengthinput-enableoutput-highbias-disableinput-disablebias-pull-updrive-strength-microampbias-pull-downoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsmemory-regionpower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-0pinctrl-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,tx-delay-psmediatek,mac-wolsnps,reset-gpiosnps,reset-delays-ussnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeuprole-switch-default-modeusb-role-switchvusb33-supplyvbus-supplyremote-endpointbus-widthmax-frequencyhs400-ds-delaycap-mmc-highspeedcap-mmc-hw-resetmmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104usb2-lpm-disablemediatek,u3p-dis-mskbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN1-supplyLDO_VIN3-supplylabeldata-roleop-sink-microwattpower-roletry-power-rolesource-pdossink-pdosmode-switchorientation-switchvcc-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathenable-active-highvin-supplyregulator-boot-onno-map