s8e(d1google,tomato-rev1google,tomatomediatek,mt8195 +7Acer Tomato (rev1) boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e00000/soc/i2c@11e01000/soc/i2c@11e02000/soc/i2c@11e03000/soc/i2c@11e04000/soc/i2c@11d00000/soc/i2c@11d02000 /soc/mmc@11230000/soc/mmc@11240000/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@100cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@200cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@300cpuarm,cortex-a55*.psci<Pec3@`4s@@cpu@400cpuarm,cortex-a78*.psci<Pf`s@@  cpu@500cpuarm,cortex-a78*.psci<Pf`s@@  cpu@600cpuarm,cortex-a78*.psci<Pf`s@@  cpu@700cpuarm,cortex-a78*.psci<Pf`s@@  cpu-mapcluster0core0 core1 core2 core3core4core5core6core7idle-statespscicpu-retention-larm,idle-state6G2X_hDcpu-retention-barm,idle-state6G-Xhcpu-off-larm,idle-state6G7XhHcpu-off-barm,idle-state6G2Xhl2-cache0cachey@l2-cache1cachey@ l3-cachecachey @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-soundokay}DL10_FEDPTX_BEETDM1_IN_BEETDM2_IN_BEETDM1_OUT_BEETDM2_OUT_BEUL_SRC1_BEAFE_SOF_DL2AFE_SOF_DL3AFE_SOF_UL4AFE_SOF_UL5default?HeadphoneHPOLHeadphoneHPORIN1PHeadset MicExt SpkSpeaker%mediatek,mt8195_mt6359_rt1019_rt56827mt8195_r1019_5682mm-dai-link ETDM1_IN_BE)cpuhs-playback-dai-link ETDM1_OUT_BE)cpucodec?hs-capture-dai-link ETDM2_IN_BE)cpucodec?spk-playback-dai-link ETDM2_OUT_BE)cpucodec?displayport-dai-linkDPTX_BEcodec?fixed-factor-clock-13mfixed-factor-clockIV]grclk13m2oscillator-26m fixed-clockIPrclk26moscillator-32k fixed-clockIPrclk32kperformance-controller@11bc10mediatek,cpufreq-hw * 0 opp-table-gpuoperating-points-v2|opp-390000000> hopp-410000000p opp-431000000 opp-4730000001h@ <opp-515000000F <opp-556000000!# Ҧopp-598000000# opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-82000000005 opp-8500000002 @opp-8800000004s qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.05smctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  *    ppi-partitionsinterrupt-partition-0. interrupt-partition-1.syscon@10000000 mediatek,mt8195-topckgensyscon*I!syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd*I7"syscon@10003000mediatek,mt8195-pericfgsyscon*0IHpinctrl@10005000mediatek,mt8195-pinctrl*PBDiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintN^jvdefault>I2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOaudio-default-pinspins-cmd-datDEFGHIJK<12345pins-hp-jack-int-odlYecr50-irq-default-pinskpins-gsc-ap-int-odlXcros-ec-irq-default-pins>pins-ec-ap-int-odleedptx-default-pinspins-cmd-datdisp-pwm0-default-pinsBpins-disp-pwmRadptx-default-pinspins-cmd-dati2c0-default-pinsbpins-bus i2c1-default-pinscpins-bus  i2c2-default-pinsfpins-bus  i2c3-default-pinsjpins-busi2c4-default-pinslpins-busi2c5-default-pins^pins-busi2c7-default-pins_pins-busmmc0-default-pinsKpins-cmd-dat$~}|{wvutyepins-clkzfpins-rstxemmc0-uhs-pinsLpins-cmd-dat$~}|{wvutyepins-clkzfpins-dsfpins-rstxemmc1-detect-pinsPpins-insert6mmc1-default-pinsOpins-cmd-datnpqrsepins-clkofnor-default-pins\pins-ck-io pins-cspcie0-default-pinspins-bus pcie1-default-pins[pins-bus panel-pwr-default-pinspins-vreg-en7pio-default-pinspins-wifi-enable:pins-low-power-pd,./0ABCDpins-low-power-pupd<MNOPSUZ[]^_`hikert1019p-default-pinspins-amp-sdbdscp-default-pins4pins-vreqLspi0-default-pins=pins-cs-mosi-clk pins-misosubpmic-default-pins`pins-subpmic-int-ntrackpad-default-pinsdpins-int-ntouchscreen-default-pinsmpins-int-n\epins-rst8pins-report-sw9syscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd*`power-controller!mediatek,mt8195-power-controller+%6power-domain@8*+%9power-domain@9* V !GmfgaltS"+%9#power-domain@10* %power-domain@11* %power-domain@12* %power-domain@13* %power-domain@14*%power-domain@15*V!!!! !@!A!K!$ $ $$$$$$$$$$$$$$$$$ Gvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18S"+%power-domain@24*V%Gvdec1-0S"%power-domain@27*V& Gvenc1-larbS"%power-domain@16*8V!'$'%'&'''(')DGvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5S"+%power-domain@17*V!((Gvppsys1vppsys1-0vppsys1-1S"%power-domain@22* V))))$Gwepsys-0wepsys-1wepsys-2wepsys-3S"%power-domain@23*V*Gvdec0-0S"%power-domain@25*V+Gvdec2-0S"%power-domain@26*V, Gvenc0-larbS"%power-domain@18* V!---&Gvdosys1vdosys1-0vdosys1-1vdosys1-2S"+%power-domain@19*S"%power-domain@20*S"%power-domain@21*V!QGhdmi_tx%power-domain@28*V..  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""IGsourcehclksource_cge! u! disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu*'V""K?@$Wlvts-calib-data-1lvts-calib-data-2husb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci *))> Dmacippc Se!.!/u!!$V1! 1$Gsys_ckref_ckmcu_ckdma_ckxhci_ck Hhokay  I J usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 **-*> Dmacippc*?+e!0u!V1!1Gsys_ckref_ckmcu_ck T Hiokay host Iusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci*Dmace!1u!V1Gsys_ckokay Jusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 *+-+> Dmacippc+?+e!2u!V1!1 Gsys_ckref_ckmcu_ck U Hjokay host Iusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci*Dmace!3u!V1 Gsys_ckokay  Jpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+*/@ Dpcie-mac 8  V 0V"V"#"&"+"K1/Gpl_250mtl_26mtl_96mtl_32kperi_26mperi_meme!Gu! W +pcie-phy6" mac 5` HXXXX disabledinterrupt-controllerXpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+*/@ Dpcie-mac 8$$ $ $  V (V"W"X"Q1/Gpl_250mtl_26mtl_96mtl_32kperi_26mperi_meme!Hu! Y +pcie-phy6" mac 5` HZZZZokaydefault[interrupt-controllerZspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor*29V!o11 Gspisfaxi+okaydefault\flash@0jedec,spi-nor*mu V gefuse@11c10000%mediatek,mt8195-efusemediatek,efuse*+usb3-tx-imp@184,1* xsusb3-rx-imp@184,2* xrusb3-intr@185* xqusb3-tx-imp@186,1* xpusb3-rx-imp@186,2* xousb3-intr@187* xnusb2-intr-p0@188,1* xusb2-intr-p1@188,2* xusb2-intr-p2@189,1* xusb2-intr-p3@189,2* xpciephy-rx-ln1@190,1* xzpciephy-tx-ln1-nmos@190,2* xypciephy-tx-ln1-pmos@191,1* xxpciephy-rx-ln0@191,2* xwpciephy-tx-ln0-nmos@192,1* xvpciephy-tx-ln0-pmos@192,2* xupciephy-glb-intr@193* xtdp-data@1ac*lvts1-calib@1bc*?lvts2-calib@1d0*8@svs-calib@580*dAsocinfo-data1@7a0*t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0*V!Gref }Tt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0*V!Gref }Udsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx*V rmipi_tx0_pllI } disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx*V rmipi_tx1_pllI } disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"]V]"; Gmaindma+okayPdefault^i2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"]V]"; Gmaindma+ disabledi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c * "]V]"; Gmaindma+okayPdefault_pmic@34mediatek,mt6360*4 IRQBdefault`clock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s*0I]i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"]Va"; Gmaindma+okayPdefaultbi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"]Va"; Gmaindma+okayP 0defaultctrackpad@15elan,ekth3000* defaultd ei2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c * "]Va"; Gmaindma+okayPdefaultfcodec@1a* Y   g h irealtek,rt5682i i2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c *0"]Va"; Gmaindma+okayPdefaultjtpm@50 google,cr50*P Xdefaultki2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c *@"]Va"; Gmaindma+okayPdefaultltouchscreen@10 hid-over-i2c*  \defaultm   .eokayclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w*PIat-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+6okayusb-phy@0* V! Grefda_ref }Susb-phy@700*V ! Grefda_ref KnopWintrrx_imptx_imp }Yt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0* V! Grefda_ref }Fusb-phy@700*V ! Grefda_ref KqrsWintrrx_imptx_imp }Gphy@11e80000mediatek,mt8195-pcie-phy*DsifKtuvwxyzGWglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln16 } disabledWufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy*V Gunipromp } disabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm*@V{0 jobmmugpu 9|(6 6 6 6 6 Mcore0core1core2core3core4okay `clock-controller@13fbf000mediatek,mt8195-mfgcfg*I{syscon@14000000mediatek,mt8195-vppsys0syscon*I l}$dma-controller@14001000mediatek,mt8195-mdp3-rdma* l}   ~6 V$<} } }}} display@14002000mediatek,mt8195-mdp3-fg*  l} V$display@14003000mediatek,mt8195-mdp3-stitch*0 l}0V$display@14004000mediatek,mt8195-mdp3-hdr*@ l}@V$"display@14005000mediatek,mt8195-mdp3-aal*PF l}PV$ 6display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*` l}` %V$ display@14007000mediatek,mt8195-mdp3-tdshp*p l}pV$#display@14008000mediatek,mt8195-mdp3-color*I l}V$$6display@14009000mediatek,mt8195-mdp3-ovl*J l}V$%6 display@1400a000mediatek,mt8195-mdp3-padding* l}V$6display@1400b000mediatek,mt8195-mdp3-tcc* l}V$dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot* l}  +V$ 6 mutex@1400f000mediatek,mt8195-vpp-mutex*P l}V$6smi@14010000mediatek,mt8195-smi-sub-common*V$$$Gapbsmigals0 6smi@14011000mediatek,mt8195-smi-sub-common*V$$$Gapbsmigals0 6smi@14012000mediatek,mt8195-smi-common-vpp*  V$$$$Gapbsmigals0gals16larb@14013000mediatek,mt8195-smi-larb*0  V$$Gapbsmi6iommu@14018000mediatek,mt8195-iommu-vpp*8 RV$Gbclk6clock-controller@14e00000mediatek,mt8195-wpesys*I)clock-controller@14e02000mediatek,mt8195-wpesys_vpp0* Iclock-controller@14e03000mediatek,mt8195-wpesys_vpp1*0Ilarb@14e04000mediatek,mt8195-smi-larb*@  V))Gapbsmi6larb@14e05000mediatek,mt8195-smi-larb*P  V))$ Gapbsmigals6syscon@14f00000mediatek,mt8195-vppsys1syscon*I l} (mutex@14f01000mediatek,mt8195-vpp-mutex*{ l} V('6larb@14f02000mediatek,mt8195-smi-larb*   V(($ Gapbsmigals6larb@14f03000mediatek,mt8195-smi-larb*0  V(($ Gapbsmigals6display@14f06000mediatek,mt8195-mdp3-split*` l} `V((+(,6display@14f07000mediatek,mt8195-mdp3-tcc*p l} pV(dma-controller@14f08000mediatek,mt8195-mdp3-rdma* l}  V( 6 dma-controller@14f09000mediatek,mt8195-mdp3-rdma* l}  V(  6 dma-controller@14f0a000mediatek,mt8195-mdp3-rdma* l}  V(  6 display@14f0b000mediatek,mt8195-mdp3-fg* l} V( display@14f0c000mediatek,mt8195-mdp3-fg* l} V( display@14f0d000mediatek,mt8195-mdp3-fg* l} V( display@14f0e000mediatek,mt8195-mdp3-hdr* l} V(display@14f0f000mediatek,mt8195-mdp3-hdr* l} V(display@14f10000mediatek,mt8195-mdp3-hdr* l} V( display@14f11000mediatek,mt8195-mdp3-aal*i l} V(6display@14f12000mediatek,mt8195-mdp3-aal* j l} V(6display@14f13000mediatek,mt8195-mdp3-aal*0k l} 0V(!6display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*@ l} @ V(display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*P l} P V($display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz*` l} ` V(%display@14f17000mediatek,mt8195-mdp3-tdshp*p l} pV(display@14f18000mediatek,mt8195-mdp3-tdshp* l} V((display@14f19000mediatek,mt8195-mdp3-tdshp* l} V()display@14f1a000mediatek,mt8195-mdp3-merge* l} V(6display@14f1b000mediatek,mt8195-mdp3-merge* l} V(6display@14f1c000mediatek,mt8195-mdp3-color*t l} V(6display@14f1d000mediatek,mt8195-mdp3-color* l} uV(6display@14f1e000mediatek,mt8195-mdp3-color*v l} V(6display@14f1f000mediatek,mt8195-mdp3-ovl*w l} V(6 display@14f20000mediatek,mt8195-mdp3-padding* l} V(6display@14f21000mediatek,mt8195-mdp3-padding* l} V(6display@14f22000mediatek,mt8195-mdp3-padding*  l} V(6dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot*0 l} 0 V( 6 dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot*@ l} @ V( 6 dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot*P l} P V( 6 clock-controller@15000000mediatek,mt8195-imgsys*I.larb@15001000mediatek,mt8195-smi-larb*  V...  Gapbsmigals6smi@15002000mediatek,mt8195-smi-sub-common* V..$Gapbsmigals0 6smi@15003000mediatek,mt8195-smi-sub-common*0V... Gapbsmigals0 6clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top*Ilarb@15120000mediatek,mt8195-smi-larb*  V.Gapbsmi6clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr*Iclock-controller@15220000mediatek,mt8195-imgsys1_wpe*"Ilarb@15230000mediatek,mt8195-smi-larb*#  V.Gapbsmi6clock-controller@15330000mediatek,mt8195-ipesys*3I/larb@15340000mediatek,mt8195-smi-larb*4  V//Gapbsmi6clock-controller@16000000mediatek,mt8195-camsys*I0larb@16001000mediatek,mt8195-smi-larb*  V000 Gapbsmigals6larb@16002000mediatek,mt8195-smi-larb*   V00Gapbsmi6smi@16004000mediatek,mt8195-smi-sub-common*@V000Gapbsmigals0 6smi@16005000mediatek,mt8195-smi-sub-common*PV00$Gapbsmigals0 6larb@16012000mediatek,mt8195-smi-larb*   VGapbsmi6 larb@16013000mediatek,mt8195-smi-larb*0  VGapbsmi6 larb@16014000mediatek,mt8195-smi-larb*@  VGapbsmi6!larb@16015000mediatek,mt8195-smi-larb*P  VGapbsmi6!clock-controller@1604f000mediatek,mt8195-camsys_rawa*Iclock-controller@1606f000mediatek,mt8195-camsys_yuva*Iclock-controller@1608f000mediatek,mt8195-camsys_rawb*Iclock-controller@160af000mediatek,mt8195-camsys_yuvb* Iclock-controller@16140000mediatek,mt8195-camsys_mraw*Ilarb@16141000mediatek,mt8195-smi-larb*  V00 Gapbsmigals6"larb@16142000mediatek,mt8195-smi-larb*   VGapbsmi6"clock-controller@17200000mediatek,mt8195-ccusys* Ilarb@17201000mediatek,mt8195-smi-larb*   VGapbsmi6video-codec@18000000mediatek,mt8195-vcodec-dec ~ + *@`video-codec@2000mediatek,mtk-vcodec-lat-soc*   V!A**!Gselvdeclattope!Au!6video-codec@10000mediatek,mtk-vcodec-lat*0  V!A**!Gselvdeclattope!Au!6video-codec@25000mediatek,mtk-vcodec-core*PP  V!A%%!Gselvdeclattope!Au!6larb@1800d000mediatek,mt8195-smi-larb*  V**Gapbsmi6larb@1800e000mediatek,mt8195-smi-larb*  V$*Gapbsmi6clock-controller@1800f000mediatek,mt8195-vdecsys_soc*I*larb@1802e000mediatek,mt8195-smi-larb*  V%%Gapbsmi6clock-controller@1802f000mediatek,mt8195-vdecsys*I%larb@1803e000mediatek,mt8195-smi-larb*  V$+Gapbsmi6clock-controller@1803f000mediatek,mt8195-vdecsys_core1*I+clock-controller@190f3000mediatek,mt8195-apusys_pll*0Iclock-controller@1a000000mediatek,mt8195-vencsys*I,larb@1a010000mediatek,mt8195-smi-larb*  V,,Gapbsmi6video-codec@1a020000mediatek,mt8195-vcodec-enc*H `abcdvwxyU ~V, Gvenc_sele!@u!6+jpgdec-mastermediatek,mt8195-jpgdec60 mnrstu+jpgdec@1a040000mediatek,mt8195-jpgdec-hw*0 mnrstuWV,Gjpgdec6jpgdec@1a050000mediatek,mt8195-jpgdec-hw*0 mnrstuXV,Gjpgdec6jpgdec@1b040000mediatek,mt8195-jpgdec-hw*0 \V&Gjpgdec6clock-controller@1b000000mediatek,mt8195-vencsys_core1*I&syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon* I l'jpgenc-mastermediatek,mt8195-jpgenc6 +jpgenc@1a030000mediatek,mt8195-jpgenc-hw* ghilVV,Gjpgenc6jpgenc@1b030000mediatek,mt8195-jpgenc-hw* [V&Gjpgenc6larb@1b010000mediatek,mt8195-smi-larb*  V&&$  Gapbsmigals6ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl*|6V'  lrdma@1c002000mediatek,mt8195-disp-rdma* ~6V'  l color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color*06V' l0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr*@6V' l@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal*P6V' lPgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma*`6V' l`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither*p6V'  lpdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi*6V''*Genginedigitalhs  +dphy disableddsc@1c009000mediatek,mt8195-disp-dsc*6V' ldsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi* 6V''+Genginedigitalhs  +dphy disabledmerge@1c014000mediatek,mt8195-disp-merge*@6V' l@dp-intf@1c015000mediatek,mt8195-dp-intf*PV',' Gpixelenginepllokayportendpoint mutex@1c016000mediatek,mt8195-disp-mutex*`6V' l` Ularb@1c018000mediatek,mt8195-smi-larb*  V'('($  Gapbsmigals6larb@1c019000mediatek,mt8195-smi-larb*  V'($ $ Gapbsmigals6syscon@1c100000mediatek,mt8195-vdosys1syscon*  lI7-smi@1c01b000mediatek,mt8195-smi-common-vdo* V'%'&')'$Gapbsmigals0gals16iommu@1c01f000mediatek,mt8195-iommu-vdo*8 V''Gbclk6mutex@1c101000mediatek,mt8195-disp-mutex* Dvdo1_mutex6V- Gvdo1_mutex l larb@1c102000mediatek,mt8195-smi-larb*   V--- Gapbsmigals6larb@1c103000mediatek,mt8195-smi-larb*0  V--$  Gapbsmigals6dma-controller@1c104000mediatek,mt8195-vdo1-rdma*@V-6 @ l@ dma-controller@1c105000mediatek,mt8195-vdo1-rdma*PV-6 ` lP dma-controller@1c106000mediatek,mt8195-vdo1-rdma*`V-6 A l` dma-controller@1c107000mediatek,mt8195-vdo1-rdma*pV-6 a lp dma-controller@1c108000mediatek,mt8195-vdo1-rdma*V-6 B l dma-controller@1c109000mediatek,mt8195-vdo1-rdma*V-6 b l dma-controller@1c10a000mediatek,mt8195-vdo1-rdma*V-6 C l dma-controller@1c10b000mediatek,mt8195-vdo1-rdma*V-6 c l vpp-merge@1c10c000mediatek,mt8195-disp-merge*V- -Gmergemerge_async6 l -vpp-merge@1c10d000mediatek,mt8195-disp-merge*V- -Gmergemerge_async6 l -vpp-merge@1c10e000mediatek,mt8195-disp-merge*V- -Gmergemerge_async6 l -vpp-merge@1c10f000mediatek,mt8195-disp-merge*V- -Gmergemerge_async6 l -vpp-merge@1c110000mediatek,mt8195-disp-merge*V- -Gmergemerge_async6 l -dp-intf@1c113000mediatek,mt8195-dp-intf*06V-/- Gpixelenginepllokayportendpoint hdr-engine@1c114000mediatek,mt8195-disp-ethdrp*@Pp4Dmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp l@PphV-%- -#-!-$-"-1-&-'-(-)-*!Gmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top6 de(-3-4-5-6-7E vdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-tx*PKWdp_calibration_data6 okaydefaultports+port@0*endpoint port@1*endpoint 0 aux-buspanel edp-panel ; Hportendpoint dp-tx@1c600000mediatek,mt8195-dp-tx*`KWdp_calibration_data6 okay defaultports+port@0*endpoint port@1*endpoint 0thermal-zonescpu0-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 cpu1-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 cpu2-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 cpu3-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 cpu4-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 cpu5-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 cpu6-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 cpu7-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0 vpu0-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalvpu1-thermal R ` v tripstrip-alert L %passivetrip-crit   %criticalgpu-thermal R ` v tripstrip-alert L %passivetrip-crit   %criticalgpu1-thermal R ` v tripstrip-alert L %passivetrip-crit   %criticalvdec-thermal R ` v tripstrip-alert L %passivetrip-crit   %criticalimg-thermal R ` v tripstrip-alert L %passivetrip-crit   %criticalinfra-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcam0-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalcam1-thermal R ` vtripstrip-alert L %passivetrip-crit   %criticalsoc-area-thermal R ` vtripstrip-crit H   %criticalpmic-area-thermal R ` vtripstrip-crit H   %criticalbacklight-lcd0pwm-backlight  @ R    ;chosenserial0:115200n8memory@40000000memory*@regulator-pp3300-disp-xregulator-fixedpp3300_disp_x2Z2Z  $7default)hregulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5442Z2Z)iregulator-pp3300-s3regulator-fixed pp3300_s3442Z2Z)heregulator-pp3300-z2regulator-fixed pp3300_z2442Z2Z)hregulator-pp4200-z2regulator-fixed pp4200_z244@@@@)regulator-pp5000-s5regulator-fixed pp5000_s544LK@LK@)regulator-ppvar-sysregulator-fixed ppvar_sys44thermal-sensor-t1generic-adc-thermalhFRsensor-channelcx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,thermal-sensor-t2generic-adc-thermalhFRsensor-channelcx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,regulator-5v0-usb-vbusregulator-fixed usb-vbusLK@LK@4Jreserved-memory+memory@50000000shared-dma-pool*P|3memory@60000000shared-dma-pool*`|:memory@60d80000shared-dma-pool*`|<memory@60e80000shared-dma-pool*`(|9rt1019prealtek,rt1019prt1019p default d compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformmediatek,adspmediatek,dai-linkpinctrl-namespinctrl-0audio-routinglink-namemediatek,clk-providersound-dai#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitgpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgassigned-clocksassigned-clock-parentsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesmediatek,etdm-in2-cowork-sourcemediatek,etdm-out2-cowork-sourcemediatek,pad-selectspi-max-frequencywakeup-sourcegoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupdr_modevusb33-supplyrx-fifo-depthvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104mediatek,u3p-dis-mskusb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsi2c-scl-internal-delay-nsvcc-supply#sound-dai-cellsrealtek,jd-srcAVDD-supplyMICVDD-supplyVBAT-supplyrealtek,btndet-delayhid-descr-addrpost-power-on-delay-msvdd-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanespower-supplybacklightpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicebrightness-levelsdefault-brightness-levelenable-gpiosnum-interpolated-stepspwmsstdout-pathenable-active-highgpiovin-supplyregulator-boot-onio-channelsio-channel-namestemperature-lookup-tableno-maplabelsdb-gpios