O8H(cH\Sedgeble,neural-compute-module-2-ioedgeble,neural-compute-module-2rockchip,rv1126&7Edgeble Neu2 IO Boardaliases=/i2c@ff3f0000B/mmc@ffc50000G/serial@ff570000cpuscpu@f00Ocpuarm,cortex-a7[_pscimtcpu@f01Ocpuarm,cortex-a7[_pscimcpu@f02Ocpuarm,cortex-a7[_pscimcpu@f03Ocpuarm,cortex-a7[_pscimarm-pmuarm,cortex-a7-pmu0{|}~psci arm,psci-1.0fsmctimerarm,armv7-timer0   n6display_subsystemrockchip,display-subsystemoscillator fixed-clockn6xin24m!syscon@fe000000&rockchip,rv1126-grfsysconsimple-mfd[ syscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfd[io-domains&rockchip,rv1126-pmu-io-voltage-domainokay     (6 D Rqos@fe860000rockchip,rv1126-qossyscon[ qos@fe860080rockchip,rv1126-qossyscon[ qos@fe860200rockchip,rv1126-qossyscon[ qos@fe86c000rockchip,rv1126-qossyscon[ qos@fe8a0000rockchip,rv1126-qossyscon[ qos@fe8a0080rockchip,rv1126-qossyscon[ qos@fe8a0100rockchip,rv1126-qossyscon[ qos@fe8a0180rockchip,rv1126-qossyscon[ interrupt-controller@feff0000 arm,gic-400`u [ @ `   power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd[>power-controller!rockchip,rv1126-power-controller-power-domain@15[8mruv power-domain@16[mopower-domain@10[ PmZ[i2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c[? m ! i2cpclkdefaultokaypmic@20rockchip,rk809[ & rk808-clkout1rk808-clkout2default %1=IU a%regulatorsDCDC_REG1 mvdd_npu_vepu| ~qregulator-state-memDCDC_REG2mvdd_arm| pqregulator-state-memDCDC_REG3mvcc_ddr|regulator-state-memDCDC_REG4 mvcc3v3_sys|2Z2Z regulator-state-mem/2ZDCDC_REG5 mvcc_buck5|!!regulator-state-mem/!LDO_REG1mvcc_0v8| 5 5regulator-state-memLDO_REG2 mvcc1v8_pmu|w@w@ regulator-state-mem/w@LDO_REG3 mvcc0v8_pmu| 5 5regulator-state-mem/ 5LDO_REG4mvcc_1v8|w@w@ regulator-state-mem/w@LDO_REG5 mvcc_dovddw@w@regulator-state-memLDO_REG6 mvcc_dvddOOregulator-state-memLDO_REG7 mvcc_avdd**regulator-state-memLDO_REG8 mvccio_sd|w@2Z regulator-state-memLDO_REG9 mvcc3v3_sd|2Z2Zregulator-state-memSWITCH_REG1mvcc_5v0SWITCH_REG2mvcc_3v3|2serial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uart[A n6m  baudclkapb_pclkKPtxrxdefaultZd disabledclock-controller@ff480000rockchip,rv1126-pmucru[H qclock-controller@ff490000rockchip,rv1126-cru[Im!xin24m qdma-controller@ff4e0000arm,pl330arm,primecell[N@~m apb_pclkserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uart[V n6mbaudclkapb_pclkKPtxrxdefault "#$Zdokaybluetoothqcom,qca9377-btm% &default'  serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uart[W n6mbaudclkapb_pclkK Ptxrxdefault(Zdokayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uart[X n6mbaudclkapb_pclkK  Ptxrxdefault)Zd disabledserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uart[Y n6mbaudclkapb_pclkK  Ptxrxdefault*Zd disabledserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uart[Z n6m baudclkapb_pclkKPtxrxdefault+Zd disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc[^ (m, saradcapb_pclk; saradc-apbokay timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timer[f  m - pclktimervop@ffb00000rockchip,rv1126-vop[  ;aclk_vopdclk_vophclk_vopm axiahbdclk, -  disabledportendpoint@0[endpoint@1[iommu@ffb00f00rockchip,iommu[ ; aclkifacem -  disabled,ethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a[@_`$macirqeth_wake_irq @m~Tstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_ref stmmaceth4EN.^/q0okay~} sY@}x@input1rgmii2default34*mdiosnps,dwmac-mdioethernet-phy@04ethernet-phy-id001c.c916ethernet-phy-ieee802.3-c22[default5N   1stmmac-axi-config,<L.rx-queues-configV/queue0tx-queues-configl0queue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc[@ N mrstbiuciuciu-driveciu-sample  -okaydefault 678Z2 mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc[@ L mlmnbiuciuciu-driveciu-sample okay default9:;<Z,9 mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc[@ M mopqbiuciuciu-driveciu-sample -okayGTj=default >?@Z9  spi@ffc90000 rockchip,sfc[@ PvĴclk_sfchclk_sfcmv -okaydefaultAflash@0jedec,spi-nor[upinctrlrockchip,rv1126-pinctrl gpio@ff460000rockchip,gpio-bank[F "m&`ugpio@ff620000rockchip,gpio-bank[b #m(`uJgpio@ff630000rockchip,gpio-bank[c $m)`ugpio@ff640000rockchip,gpio-bank[d %m*`u&gpio@ff650000rockchip,gpio-bank[e &m +`upcfg-pull-upEpcfg-pull-downDpcfg-pull-noneBpcfg-pull-none-drv-level-3Gpcfg-pull-up-drv-level-2Cpcfg-pull-none-drv-level-0-smtFclk_out_ethernetclk-out-ethernetm1-pins&B4emmcemmc-bus8&CCCCCCCC6emmc-clk&C8emmc-cmd&C7fspifspi-pins`&DEEEEEAi2c0i2c0-xfer & F Frgmiirgmiim1-pins&BBB BBBB BGGGGGG3sdmmc0sdmmc0-bus4@&CCCC;sdmmc0-clk&C9sdmmc0-cmd& C:sdmmc0-det&B<sdmmc1sdmmc1-bus4@& C CCC@sdmmc1-clk& C>sdmmc1-cmd& C?uart0uart0-xfer &EE"uart0-ctsn&B#uart0-rtsn&B$uart1uart1m0-xfer &EEuart2uart2m1-xfer &EE(uart3uart3m0-xfer &EE)uart4uart4m0-xfer &EE*uart5uart5m0-xfer &EE+btbt-enable&B'flashflash-vol-sel& BHpmicpmic-int-l& Ewifiwifi-enable-h&BIetherneteth-phy-rst&D5vccio-flash-regulatorregulator-fixed4 G defaultH mvccio_flash|w@w@L2 pwrseq-sdiommc-pwrseq-simplem% ext_clockdefaultI  J=chosenWserial2:1500000n8vcc12v-dcin-regulatorregulator-fixed mvcc12v_dcin|Kvcc5v0-sys-regulatorregulator-fixed mvcc5v0_sys|LK@LK@LKv3v3-sys-regulatorregulator-fixed mv3v3_sys|2Z2ZL #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0mmc0serial2device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#reset-cells#dma-cellsarm,pl330-periph-burstenable-gpiosmax-speedvddxo-supplyvddio-supply#io-channel-cellsresetsreset-namesvref-supplyiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsenable-active-highgpiovin-supplystdout-path