986(36)STMicroelectronics STM32F769-DISCO board !st,stm32f769-discost,stm32f769interrupt-controller@e000e100!arm,armv7m-nvic,AR Vtimer@e000e010!arm,armv7m-systickR^okay esoc !simple-busl}timers@40000000!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@1!st,stm32-timer-triggerR ^disabledtimers@40000400!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@2!st,stm32-timer-triggerR ^disabledtimers@40000800!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@3!st,stm32-timer-triggerR ^disabledtimers@40000c00!st,stm32-timerR@  e^okay2timers@40001000!st,stm32-timersR@ eint ^disabledtimer@5!st,stm32-timer-triggerR ^disabledtimers@40001400!st,stm32-timersR@ eint ^disabledtimer@6!st,stm32-timer-triggerR ^disabledtimers@40001800!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@11!st,stm32-timer-triggerR  ^disabledtimers@40001c00!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimers@40002000!st,stm32-timersR@  eint ^disabledpwm !st,stm32-pwm ^disabledrtc@40002800 !st,stm32-rtcR@( e  l ^okayserial@40004400!st,stm32f7-uartR@D& e ^disabledserial@40004800!st,stm32f7-uartR@H' e ^disabledserial@40004c00!st,stm32f7-uartR@L4 e ^disabledserial@40005000!st,stm32f7-uartR@P5 e ^disabledi2c@40005400!st,stm32f7-i2cR@T  e^okaydefault i2c@40005800!st,stm32f7-i2cR@X!" e ^disabledi2c@40005c00!st,stm32f7-i2cR@\HI e ^disabledi2c@40006000!st,stm32f7-i2cR@`_` e ^disabledcec@40006c00 !st,stm32-cecR@l^e cechdmi-cec^okaydefaultserial@40007800!st,stm32f7-uartR@xR e ^disabledserial@40007c00!st,stm32f7-uartR@|S e ^disabledtimers@40010000!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@0!st,stm32-timer-triggerR ^disabledtimers@40010400!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@7!st,stm32-timer-triggerR ^disabledserial@40011000!st,stm32f7-uartR@% e^okaydefaultserial@40011400!st,stm32f7-uartR@G e ^disabledmmc@40011c00!arm,pl180arm,primecell%R@ e apb_pclkg<l^okayJ V _defaultopendrain i smmc@40012c00!arm,pl180arm,primecell%R@, e apb_pclk1<l ^disabledsyscon@40013800!st,stm32-syscfgsysconR@8Vinterrupt-controller@40013c00!st,stm32-exti,AR@<8 ()*>LVtimers@40014000!st,stm32-timersR@@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@8!st,stm32-timer-triggerR ^disabledtimers@40014400!st,stm32-timersR@D eint ^disabledpwm !st,stm32-pwm ^disabledtimers@40014800!st,stm32-timersR@H eint ^disabledpwm !st,stm32-pwm ^disabledpower-config@40007000!st,stm32-power-configsysconR@pVcrc@40023000!st,stm32f7-crcR@0 e  ^disabledrcc@40023800}/!st,stm32f769-rccst,stm32f746-rccst,stm32-rccR@8e  B@Vdma-controller@40026000 !st,stm32-dmaR@` / e ^disableddma-controller@40026400 !st,stm32-dmaR@d 89:;<DEF e ^disabledusb@40040000!st,stm32f7-hsotgR@M eotg  @@@@ ^okayotg usb2-phydefaultusb@50000000!st,stm32f4x9-fsotgRPC e'otg ^disabledpinctrl@40020000 }@0l!st,stm32f769-pinctrlgpio@40020000 ,AR e%GPIOAVgpio@40020400 ,AR e%GPIOBgpio@40020800 ,AR e%GPIOCgpio@40020c00 ,AR  e%GPIODgpio@40021000 ,AR e%GPIOEgpio@40021400 ,AR e%GPIOFgpio@40021800 ,AR e%GPIOGgpio@40021c00 ,AR e%GPIOHgpio@40022000 ,AR  e%GPIOIV gpio@40022400 ,AR$ e %GPIOJVgpio@40022800 ,AR( e %GPIOKcec-0Vpins29CTusart1-0Vpins12 Ta9pins22 Tusart1-1pins12 Ta9pins22Ti2c1-0Vpins2TC9usbotg-hs-0Vpins02t          Ta9usbotg-hs-1pins02t "          Ta9usbotg-fs-0pins 2 Ta9sdio-pins-a-0pins2( ) * + , 2 a9sdio-pins-od-a-0pins12( ) * + , a9pins222 C9sdio-pins-b-0V pins2i j   6 7 a9sdio-pins-od-b-0V pins12i j   6 a9pins227 C9can1-0pins12 pins22 qcan1-1pins12 pins22 qcan1-2pins121 pins220 qcan1-3pins12} pins22~ qcan2-0pins12 pins22 qcan2-1pins12 pins22 qcan3-0pins12 pins22 qcan3-1pins12 pins22 qclocksclk-hse !fixed-clock~}x@V clk-lse !fixed-clock~clk-lsi !fixed-clock~}clk-i2s-ckin !fixed-clock~lV chosenroot=/dev/ramserial0:115200n8memory@c0000000memoryRaliases/soc/serial@40011000leds !gpio-ledsled-green Y heartbeatled-red Y gpio-keys !gpio-keysbutton-0Userf Yusb-phy!usb-nop-xceiv e main_clkVmmc_vcard!regulator-fixed mmc_vcard2Z2ZV #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclocksinterrupt-parentrangesclock-names#pwm-cellsinterruptsassigned-clocksassigned-clock-parentsst,syscfgresetspinctrl-0pinctrl-namesi2c-scl-rising-time-nsi2c-scl-falling-time-nsarm,primecell-periphidmax-frequencyvmmc-supplycd-gpiosbroken-cdpinctrl-1bus-width#reset-cells#clock-cellsassigned-clock-rates#dma-cellsst,mem2memg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modephysphy-namesgpio-controller#gpio-cellsst,bank-namepinmuxslew-ratedrive-open-drainbias-disabledrive-push-pullbias-pull-upclock-frequencybootargsstdout-pathdevice_typeserial0linux,default-triggerautorepeatlabellinux,code#phy-cellsregulator-nameregulator-min-microvoltregulator-max-microvolt