GE8@0(?Sedgeble,neural-compute-module-2-ioedgeble,neural-compute-module-2rockchip,rv1126&7Edgeble Neu2 IO Boardaliases=/i2c@ff3f0000B/mmc@ffc50000G/serial@ff570000cpuscpu@f00Ocpuarm,cortex-a7[_pscimtcpu@f01Ocpuarm,cortex-a7[_pscimcpu@f02Ocpuarm,cortex-a7[_pscimcpu@f03Ocpuarm,cortex-a7[_pscimarm-pmuarm,cortex-a7-pmu0{|}~psci arm,psci-1.0fsmctimerarm,armv7-timer0   n6oscillator fixed-clockn6xin24msyscon@fe000000&rockchip,rv1126-grfsysconsimple-mfd[syscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfd[io-domains&rockchip,rv1126-pmu-io-voltage-domainokay    " 0 > L qos@fe860000rockchip,rv1126-qossyscon[ qos@fe860080rockchip,rv1126-qossyscon[ qos@fe860200rockchip,rv1126-qossyscon[ qos@fe86c000rockchip,rv1126-qossyscon[ interrupt-controller@feff0000 arm,gic-400Zo [ @ `   power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd[>power-controller!rockchip,rv1126-power-controller/power-domain@15[8mruv power-domain@16[moi2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c[? m ! i2cpclkdefaultokaypmic@20rockchip,rk809[ & rk808-clkout1rk808-clkout2default+7CO [ regulatorsDCDC_REG1 gvdd_npu_vepuv ~qregulator-state-memDCDC_REG2gvdd_armv pqregulator-state-memDCDC_REG3gvcc_ddrvregulator-state-memDCDC_REG4 gvcc3v3_sysv2Z2Z regulator-state-mem)2ZDCDC_REG5 gvcc_buck5v!!regulator-state-mem)!LDO_REG1gvcc_0v8v 5 5regulator-state-memLDO_REG2 gvcc1v8_pmuvw@w@regulator-state-mem)w@LDO_REG3 gvcc0v8_pmuv 5 5regulator-state-mem) 5LDO_REG4gvcc_1v8vw@w@ regulator-state-mem)w@LDO_REG5 gvcc_dovddw@w@ regulator-state-memLDO_REG6 gvcc_dvddOOregulator-state-memLDO_REG7 gvcc_avdd**regulator-state-memLDO_REG8 gvccio_sdvw@2Z regulator-state-memLDO_REG9 gvcc3v3_sdv2Z2Zregulator-state-memSWITCH_REG1gvcc_5v0SWITCH_REG2gvcc_3v3v+serial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uart[A n6m  baudclkapb_pclkEJtxrxdefaultT^ disabledclock-controller@ff480000rockchip,rv1126-pmucru[Hkclock-controller@ff490000rockchip,rv1126-cru[Imxin24mkdma-controller@ff4e0000arm,pl330arm,primecell[N@xm apb_pclkserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uart[V n6mbaudclkapb_pclkEJtxrxdefault T^okaybluetoothqcom,qca9377-btm  !default"  serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uart[W n6mbaudclkapb_pclkE Jtxrxdefault#T^okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uart[X n6mbaudclkapb_pclkE  Jtxrxdefault$T^ disabledserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uart[Y n6mbaudclkapb_pclkE  Jtxrxdefault%T^ disabledserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uart[Z n6m baudclkapb_pclkEJtxrxdefault&T^ disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc[^ (m, saradcapb_pclk; saradc-apbokay timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timer[f  m - pclktimerethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a[@_`macirqeth_wake_irq@m~Tstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_ref stmmaceth &'6(I)okay\~l} sY@}x@input*rgmii+default,-*mdiosnps,dwmac-mdioethernet-phy@04ethernet-phy-id001c.c916ethernet-phy-ieee802.3-c22[default.N  *stmmac-axi-config$'rx-queues-config.(queue0tx-queues-configD)queue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc[@ N mrstbiuciuciu-driveciu-sampleZe s/okaydefault0123Z+ mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc[@ L mlmnbiuciuciu-driveciu-sampleZe okaydefault4567Z mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc[@ M mopqbiuciuciu-driveciu-sampleZes/okay-:P8default 9:;Z  pinctrlrockchip,rv1126-pinctrl[hgpio@ff460000rockchip,gpio-bank[F "m&oZogpio@ff620000rockchip,gpio-bank[b #m(oZoDgpio@ff630000rockchip,gpio-bank[c $m)oZogpio@ff640000rockchip,gpio-bank[d %m*oZo!gpio@ff650000rockchip,gpio-bank[e &m +oZopcfg-pull-up@pcfg-pull-downApcfg-pull-none<pcfg-pull-none-drv-level-3?pcfg-pull-up-drv-level-2=pcfg-pull-none-drv-level-0-smt>clk_out_ethernetclk-out-ethernetm1-pins<-emmcemmc-rstnout<3emmc-bus8========0emmc-clk=2emmc-cmd=1i2c0i2c0-xfer  > >rgmiirgmiim1-pins<<< <<<< <??????,sdmmc0sdmmc0-bus4@====6sdmmc0-clk=4sdmmc0-cmd =5sdmmc0-det<7sdmmc1sdmmc1-bus4@ = ===;sdmmc1-clk =9sdmmc1-cmd =:uart0uart0-xfer @@uart0-ctsn<uart0-rtsn<uart1uart1m0-xfer @@uart2uart2m1-xfer @@#uart3uart3m0-xfer @@$uart4uart4m0-xfer @@%uart5uart5m0-xfer @@&btbt-enable<"flashflash-vol-sel <Bpmicpmic-int-l @wifiwifi-enable-h<Cetherneteth-phy-rstA.vcc5v0-sys-regulatorregulator-fixed gvcc5v0_sysvLK@LK@vccio-flash-regulatorregulator-fixed  defaultB gvccio_flashvw@w@+ pwrseq-sdiommc-pwrseq-simplem  ext_clockdefaultC D8chosen serial2:1500000n8 #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0mmc0serial2device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#reset-cells#dma-cellsarm,pl330-periph-burstenable-gpiosmax-speedvddxo-supplyvddio-supply#io-channel-cellsresetsreset-namesvref-supplyinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencypower-domainsbus-widthnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsenable-active-highgpiovin-supplystdout-path