o8|( D*chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]@krr cpu@501#cpuarm,cortex-a12/3:N]@krr cpu@502#cpuarm,cortex-a12/3:N]@krr cpu@503#cpuarm,cortex-a12/3:N]@krr opp-table-0operating-points-v2opp-126000000 opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ka  1pclktimerdisplay-subsystemrockchip,display-subsystem= mmc@ff0c0000rockchip,rk3288-dw-mshcCр kDrv1biuciuciu-driveciu-sampleQ / @3\resethokayoydefault mmc@ff0d0000rockchip,rk3288-dw-mshcCр kEsw1biuciuciu-driveciu-sampleQ !/ @3\reset hdisabledmmc@ff0e0000rockchip,rk3288-dw-mshcCр kFtx1biuciuciu-driveciu-sampleQ "/@3\reset hdisabledmmc@ff0f0000rockchip,rk3288-dw-mshcCр kGuy1biuciuciu-driveciu-sampleQ #/@3\resethokayoy,;defaultsaradc@ff100000rockchip,saradc/ $IkI[1saradcapb_pclk3W \saradc-apb hdisabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spikAR1spiclkapb_pclk[  `txrx ,default/ hdisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spikBS1spiclkapb_pclk[ `txrx -default !/ hdisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spikCT1spiclkapb_pclk[`txrx .default"#$%/ hdisabledi2c@ff140000rockchip,rk3288-i2c/ >1i2ckMdefault&hokayak8963@dasahi-kasei,ak8975/ &'default(jul3g4200d@69st,l3g4200d-gyro/ijmma8452@1d fsl,mma8452/&'default)i2c@ff150000rockchip,rk3288-i2c/ ?1i2ckOdefault*hokayi2c@ff160000rockchip,rk3288-i2c/ @1i2ckPdefault+hokayi2c@ff170000rockchip,rk3288-i2c/ A1i2ckQdefault,hokaysserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7kMU1baudclkapb_pclk[`txrxdefault-hokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8kNV1baudclkapb_pclk[`txrxdefault.hokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9kOW1baudclkapb_pclkdefault/hokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :kPX1baudclkapb_pclk[`txrxdefault0hokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;kQY1baudclkapb_pclk[  `txrxdefault1hokaydma-controller@ff250000arm,pl330arm,primecell/%@k 1apb_pclkthermal-zonesreserve-thermal2cpu-thermald2tripscpu_alert0%p1*passive3cpu_alert1%$1*passive4cpu_crit%_1 *criticalcooling-mapsmap0<30Amap1<40Agpu-thermald2tripsgpu_alert0%p1*passive5gpu_crit%_1 *criticalcooling-mapsmap0<5 A6tsadc@ff280000rockchip,rk3288-tsadc/( %kHZ1tsadcapb_pclk3 \tsadc-apbinitdefaultsleep7P8Z7dz9shokay2ethernet@ff290000rockchip,rk3288-gmac/)macirqeth_wake_irqz98kfgc]M1stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B \stmmacethhokay:rgmiiinput ; ''B@<L<default=c0lusb@ff500000 generic-ehci/P ku>zusb hdisabledusb@ff520000 generic-ohci/R )ku>zusb hdisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T k1otghostu? zusb2-phy hdisabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X k1otgotg@@ u@ zusb2-phyhokayusb@ff5c0000 generic-ehci/\ k hdisableddma-controller@ff600000arm,pl330arm,primecell/`@k 1apb_pclk hdisabledi2c@ff650000rockchip,rk3288-i2c/e <1i2ckLdefaultAhokaypmic@1brockchip,rk808/&BdefaultCDxin32krk808-clkout2EEE&E2E>EJFVboE|regulatorsDCDC_REG1 qpvdd_arm regulator-state-memDCDC_REG2 Pvdd_gpuregulator-state-memB@DCDC_REG3vcc_ddrregulator-state-memDCDC_REG42Z2Zvcc_ioregulator-state-mem2ZLDO_REG12Z2Zvcc_lan:regulator-state-mem2ZLDO_REG2w@2Z vccio_sdregulator-state-memLDO_REG3B@B@vdd_10regulator-state-memB@LDO_REG4w@w@ vcc18_lcdregulator-state-memw@LDO_REG5w@2Zldo5LDO_REG6B@B@ vdd10_lcdregulator-state-memB@LDO_REG7w@w@vcc_18Fregulator-state-memw@LDO_REG82Z2Zvcca_33Zregulator-state-mem2ZSWITCH_REG1 vccio_wl\regulator-state-memSWITCH_REG2vcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2c/f =1i2ckNdefaultGhokaypwm@ff680000rockchip,rk3288-pwm/h;defaultHk_ hdisabledpwm@ff680010rockchip,rk3288-pwm/h;defaultIk_ hdisabledpwm@ff680020rockchip,rk3288-pwm/h ;defaultJk_ hdisabledpwm@ff680030rockchip,rk3288-pwm/h0;defaultKk_ hdisabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controllerF<hL `power-domain@9/ kchgfdehilkj$ZLMNOPQRSTFpower-domain@11/ kopZUVFpower-domain@12/ kZWFpower-domain@13/ kZXYFreboot-modesyscon-reboot-modeahRBtRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/vk 1xin24mz9H<jk$#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w9edp-phyrockchip,rk3288-dp-phykh124m hdisabledpio-domains"rockchip,rk3288-io-voltage-domainhokayZ[: '3A\usbphyrockchip,rk3288-usb-phyhokayusb-phy@320/ k]1phyclk3 \phy-reset@usb-phy@334/4k^1phyclk3 \phy-reset>usb-phy@348/Hk_1phyclk3 \phy-reset?watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/kp O hdisabledsound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/MkT 1mclkhclk[]`tx 6default^z9 hdisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/M 5kR1i2s_clki2s_hclk[]]`txrxdefault_^y hdisabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 k}1aclkhclksclkapb_pclk3 \crypto-rstiommu@ff900800rockchip,iommu/@ k 1aclkiface hdisablediommu@ff914000rockchip,iommu /@P k 1aclkiface hdisabledrga@ff920000rockchip,rk3288-rga/ kj1aclkhclksclk` 3ilm \coreaxiahbvop@ff930000rockchip,rk3288-vop / k1aclk_vopdclk_vophclk_vop` 3def \axiahbdclkahokayport endpoint@0/btendpoint@1/cqendpoint@2/dkendpoint@3/eniommu@ff930300rockchip,iommu/ k 1aclkiface` hokayavop@ff940000rockchip,rk3288-vop / k1aclk_vopdclk_vophclk_vop` 3 \axiahbdclkfhokayport endpoint@0/guendpoint@1/hrendpoint@2/ilendpoint@3/joiommu@ff940300rockchip,iommu/ k 1aclkiface` hokayfdsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ k~d 1refpclk` z9 hdisabledportsport@0/endpoint@0/kdendpoint@1/liport@1/lvds@ff96c000rockchip,rk3288-lvds/@kg 1pclk_lvdslcdcm` z9 hdisabledportsport@0/endpoint@0/neendpoint@1/ojport@1/dp@ff970000rockchip,rk3288-dp/@ bkic1dppclkupzdp` 3o\dpz9 hdisabledportsport@0/endpoint@0/qcendpoint@1/rhport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/ gkhmn1iahbisfrcec` z9Mhokaysportsport@0/endpoint@0/tbendpoint@1/ugport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   vepuvdpuk 1aclkhclkv` iommu@ff9a0800rockchip,iommu/ k 1aclkiface` viommu@ff9c0440rockchip,iommu /@@@ ok 1aclkiface hdisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ jobmmugpuk:wN`  hdisabled6opp-table-1operating-points-v2wopp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ Xqos@ffaa0080rockchip,rk3288-qossyscon/ Yqos@ffad0000rockchip,rk3288-qossyscon/ Mqos@ffad0100rockchip,rk3288-qossyscon/ Nqos@ffad0180rockchip,rk3288-qossyscon/ Oqos@ffad0400rockchip,rk3288-qossyscon/ Pqos@ffad0480rockchip,rk3288-qossyscon/ Qqos@ffad0500rockchip,rk3288-qossyscon/ Lqos@ffad0800rockchip,rk3288-qossyscon/ Rqos@ffad0880rockchip,rk3288-qossyscon/ Sqos@ffad0900rockchip,rk3288-qossyscon/ Tqos@ffae0000rockchip,rk3288-qossyscon/ Wqos@ffaf0000rockchip,rk3288-qossyscon/ Uqos@ffaf0080rockchip,rk3288-qossyscon/ Vdma-controller@ffb20000arm,pl330arm,primecell/@k 1apb_pclk]efuse@ffb40000rockchip,rk3288-efuse/ kq 1pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400 @/ @ `   pinctrlrockchip,rk3288-pinctrlz9gpio@ff750000rockchip,gpio-bank/u Qk@  " Bgpio@ff780000rockchip,gpio-bank/x RkA  " gpio@ff790000rockchip,gpio-bank/y SkB  " gpio@ff7a0000rockchip,gpio-bank/z TkC  " gpio@ff7b0000rockchip,gpio-bank/{ UkD  " ;gpio@ff7c0000rockchip,gpio-bank/| VkE  " gpio@ff7d0000rockchip,gpio-bank/} WkF  " gpio@ff7e0000rockchip,gpio-bank/~ XkG  " gpio@ff7f0000rockchip,gpio-bank/ YkH  " 'hdmihdmi-cec-c0 .xhdmi-cec-c7 .xhdmi-ddc .xxhdmi-ddc-unwedge .yxpcfg-output-low <ypcfg-pull-up Gzpcfg-pull-down T{pcfg-pull-none cxpcfg-pull-none-12ma c p |suspendglobal-pwroff .xDddrio-pwroff .xddr0-retention .zddr1-retention .zedpedp-hpd . {i2c0i2c0-xfer .xxAi2c1i2c1-xfer .xx&i2c2i2c2-xfer . x xGi2c3i2c3-xfer .xx*i2c4i2c4-xfer .xx+i2c5i2c5-xfer .xx,i2s0i2s0-bus` .xxxxxx_lcdclcdc-ctl@ .xxxxmsdmmcsdmmc-clk .x sdmmc-cmd .zsdmmc-cd .zsdmmc-bus1 .zsdmmc-bus4@ .zzzzsdmmc-pwr . xsdio0sdio0-bus1 .zsdio0-bus4@ .zzzzsdio0-cmd .zsdio0-clk .xsdio0-cd .zsdio0-wp .zsdio0-pwr .zsdio0-bkpwr .zsdio0-int .zsdio1sdio1-bus1 .zsdio1-bus4@ .zzzzsdio1-cd .zsdio1-wp .zsdio1-bkpwr .zsdio1-int .zsdio1-cmd .zsdio1-clk .xsdio1-pwr . zemmcemmc-clk .xemmc-cmd .zemmc-pwr . zemmc-bus1 .zemmc-bus4@ .zzzzemmc-bus8 .zzzzzzzzspi0spi0-clk . zspi0-cs0 . zspi0-tx .zspi0-rx .zspi0-cs1 .zspi1spi1-clk . zspi1-cs0 . z!spi1-rx .z spi1-tx .zspi2spi2-cs1 .zspi2-clk .z"spi2-cs0 .z%spi2-rx .z$spi2-tx . z#uart0uart0-xfer .zx-uart0-cts .zuart0-rts .xuart1uart1-xfer .z x.uart1-cts . zuart1-rts . xuart2uart2-xfer .zx/uart3uart3-xfer .zx0uart3-cts . zuart3-rts . xuart4uart4-xfer .zx1uart4-cts . zuart4-rts . xtsadcotp-pin . x7otp-out . x8pwm0pwm0-pin .xHpwm1pwm1-pin .xIpwm2pwm2-pin .xJpwm3pwm3-pin .xKgmacrgmii-pins .xxxx||||xxx ||xx=rmii-pins .xxxxxxxxxxspdifspdif-tx . x^ak8963comp-int .z(buttonspwrbtn .z}dvpdvp-pwr .xirir-int .z~mma8452gsensor-int .z)pmicpmic-int .zCmemory@0#memory/external-gmac-clock fixed-clocksY@ ext_gmac<gpio-keys gpio-keys default}key-power B t GPIO Key Power  dir-receivergpio-ir-receiver Bdefault~flash-regulatorregulator-fixed vcc_flashw@w@ sdmmc-regulatorregulator-fixed   defaultvcc_sd2Z2Z  vsys-regulatorregulator-fixedvcc_sysLK@LK@Evcc18-dvp-regulatorregulator-fixed vcc18-dvpw@w@ [vcc28-dvp-regulatorregulator-fixed   Bdefault vcc28_dvp**  #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-ddr-1_8vmmc-hs200-1_8vnon-removable#io-channel-cellsdmasdma-namesvdd-supplyvid-supplyst,drdy-int-pinvddio-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typedebounce-intervalvin-supplystartup-delay-usenable-active-high