M8G(G!,Rockchip RK3228 Evaluation board$2rockchip,rk3228-evbrockchip,rk3228aliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu2arm,cortex-a7fjq@pscicpu@f01Zcpu2arm,cortex-a7fjqpscicpu@f02Zcpu2arm,cortex-a7fjqpscicpu@f03Zcpu2arm,cortex-a7fjqpsciopp_table02operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxamba 2simple-buspdma@110f00002arm,pl330arm,primecellf@ apb_pclkarm-pmu2arm,cortex-a7-pmu0LMNO%psci2arm,psci-1.0arm,psci-0.2smctimer2arm,armv7-timer80   \n6oscillator 2fixed-clock\n6lxin24mi2s1@100b0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ i2s_clki2s_hclkQtxrxdefault  disabledi2s0@100c0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf @ i2s_clki2s_hclkP  txrx disabledspdif@100d00002rockchip,rk3228-spdiff  S mclkhclk txdefault  disabledi2s2@100e0000(2rockchip,rk3228-i2srockchip,rk3066-i2sf@ i2s_clki2s_hclkRtxrx disabledsyscon@110000002sysconsimple-mfdfio-domains"2rockchip,rk3228-io-voltage-domain disabledusb2-phy@7602rockchip,rk3228-usb2phyf` phyclk lusb480m_phy0 disabled.otg-port$;<=otg-bvalidotg-idlinestate disabled-host-port > linestate disabled/usb2-phy@8002rockchip,rk3228-usb2phyf phyclk lusb480m_phy1 disabled0otg-port D linestate disabled1host-port E linestate disabled2serial@110100002snps,dw-apb-uartf 7\n6MUbaudclkapb_pclkdefault   disabledserial@110200002snps,dw-apb-uartf 8\n6NVbaudclkapb_pclkdefault disabledserial@110300002snps,dw-apb-uartf 9\n6OWbaudclkapb_pclkdefaultokayefuse@110400002rockchip,rk3228-efusef G pclk_efuseid@7fcpu_leakage@17fi2c@110500002rockchip,rk3228-i2cf $i2cLdefault disabledi2c@110600002rockchip,rk3228-i2cf %i2cMdefault disabledi2c@110700002rockchip,rk3228-i2cf &i2cNdefault disabledi2c@110800002rockchip,rk3228-i2cf 'i2cOdefault disabledspi@110900002rockchip,rk3228-spif  1ARspiclkapb_pclkdefault disabledwatchdog@110a0000 2snps,dw-wdtf  (b disabledpwm@110b00002rockchip,rk3288-pwmf ^pwmdefault disabledpwm@110b00102rockchip,rk3288-pwmf ^pwmdefault disabledpwm@110b00202rockchip,rk3288-pwmf ^pwmdefault disabledpwm@110b00302rockchip,rk3288-pwmf 0^pwmdefault disabledtimer@110c0000,2rockchip,rk3228-timerrockchip,rk3288-timerf  + a timerpclkclock-controller@110e00002rockchip,rk3228-crufHkb$!#g0,eррxhррxhthermal-zonescpu-thermal6dLZtripscpu_alert0jpvapassive cpu_alert1j$vapassive!cpu_critj_v acriticalcooling-mapsmap0  map1! tsadc@111500002rockchip,rk3228-tsadcf :HXtsadcapb_pclkH!jW tsadc-apbinitdefaultsleep"#"sokaygpu@20000000"2rockchip,rk3228-maliarm,mali-400f Hgpgpmmupp0ppmmu0pp1ppmmu1 corebusj~ disablediommu@200208002rockchip,iommuf   vpu_mmu disablediommu@200304802rockchip,iommuf @ @  vdec_mmu disablediommu@20053f002rockchip,iommuf ?  vop_mmu disablediommu@200708002rockchip,iommuf  iep_mmu disableddwmmc@3000000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Drvbiuciuciu_drvciu_sample default $%& disableddwmmc@3001000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Eswbiuciuciu_drvciu_sample default '() disableddwmmc@3002000002rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ \<4`+<4` Guybiuciuciu_drvciu_sample9C default *+,jSresetokayXjwusb@3004000022rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 otgotg@ - usb2-phy disabledusb@30080000 2generic-ehcif0  . usbhostutmi/usb disabledusb@300a0000 2generic-ohcif0   . usbhostutmi/usb disabledusb@300c0000 2generic-ehcif0   0 usbhostutmi1usb disabledusb@300e0000 2generic-ohcif0  0 usbhostutmi1usb disabledusb@30100000 2generic-ehcif0 B 02usb usbhostutmi disabledusb@30120000 2generic-ohcif0 C 0 usbhostutmi2usb disabledethernet@302000002rockchip,rk3228-gmacf0  macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 stmmacethokay|!output3rmii4mdio2snps,dwmac-mdiophy@042ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22fj? 4interrupt-controller@32010000 2arm,gic-4004 f22 2@ 2`   pinctrl2rockchip,rk3228-pinctrlgpio0@111100002rockchip,gpio-bankf 3@EU4gpio1@111200002rockchip,gpio-bankf 4AEU4gpio2@111300002rockchip,gpio-bankf 5BEU4gpio3@111400002rockchip,gpio-bankf 6CEU4pcfg-pull-upa7pcfg-pull-downnpcfg-pull-none}6pcfg-pull-none-drv-12ma 5sdmmcsdmmc-clk5$sdmmc-cmd5%sdmmc-bus4@5555&sdiosdio-clk5'sdio-cmd5(sdio-bus4@5555)emmcemmc-clk6*emmc-cmd6+emmc-bus866666666,gmacrgmii-pins6 665555 5 56666 66rmii-pins6 6655 56666phy-pins 66i2c0i2c0-xfer 66i2c1i2c1-xfer 66i2c2i2c2-xfer 66i2c3i2c3-xfer 66spi-0spi0-clk 7spi0-cs07spi0-tx 7spi0-rx 7spi0-cs1 7spi-1spi1-clk7spi1-cs07spi1-rx7spi1-tx7spi1-cs17i2s1i2s1-bus6 6 6 6 66666 pwm0pwm0-pin6pwm1pwm1-pin6pwm2pwm2-pin 6pwm3pwm3-pin 6spdifspdif-tx6 tsadcotp-gpio6"otp-out6#uart0uart0-xfer 66 uart0-cts6 uart0-rts6 uart1uart1-xfer  6 6uart1-cts6uart1-rts 6uart2uart2-xfer 76uart21-xfer  7 6uart2-cts6uart2-rts6memory@60000000Zmemoryf`@vcc-phy-regulator2regulator-fixedvcc_phyw@w@ 3 #address-cells#size-cellsinterrupt-parentmodelcompatibleserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsdmasdma-namespinctrl-namespinctrl-0statusinterrupt-names#phy-cellsreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityiommu-cellsfifo-depthmax-frequencybus-widthdefault-sample-phasecap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmaphysphy-namesclock_in_outphy-supplyphy-modephy-handlephy-is-integratedinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsenable-active-highregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-on