$8(,/isee,omap3-igep0030-rev-gti,omap36xxti,omap3&*7IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000memorylmemoryx cpuscpu@0arm,cortex-a8lcpux|cpus 'O 57pmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busxh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busx  pinmux@30 ti,omap3-padconfpinctrl-singlex08pinmux_uart1_pins+RL?Epinmux_uart3_pins+np?Epinmux_mcbsp2_pins + ?Epinmux_mmc1_pins0+?Epinmux_mmc2_pins0+(*,.02?Epinmux_smsc9221_pins+pinmux_i2c1_pins+?Epinmux_i2c3_pins+?Epinmux_twl4030_pins+A?Epinmux_uart2_pins +<>@B?Epinmux_lbep5clwmc_pins+46:?Epinmux_leds_pins+?Escm_conf@270sysconxp0?Eclocksmcbsp5_mux_fckMti,composite-mux-clock|Zxh?Emcbsp5_fckMti,composite-clock|mcbsp1_mux_fckMti,composite-mux-clock|Zx?Emcbsp1_fckMti,composite-clock|mcbsp2_mux_fckMti,composite-mux-clock| Zx? E mcbsp2_fckMti,composite-clock| mcbsp3_mux_fckMti,composite-mux-clock| xh? E mcbsp3_fckMti,composite-clock| mcbsp4_mux_fckMti,composite-mux-clock| Zxh?Emcbsp4_fckMti,composite-clock|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \pinmux_twl4030_vpins +?Eaes@480c5000 ti,omap3-aesaesxH PPgABltxrxprm@48306000 ti,omap3-prmxH0`@ clocksvirt_16_8m_ckM fixed-clockvY?Eosc_sys_ckM ti,mux-clock|x @?Esys_ckMti,divider-clock|Zxp?Esys_clkout1Mti,gate-clock|x pZdpll3_x2_ckMfixed-factor-clock|dpll3_m2x2_ckMfixed-factor-clock|?Edpll4_x2_ckMfixed-factor-clock|corex2_fckMfixed-factor-clock|?Ewkup_l4_ickMfixed-factor-clock|?LELcorex2_d3_fckMfixed-factor-clock|?Ecorex2_d5_fckMfixed-factor-clock|?Eclockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclkM fixed-clockvomap_32k_fckM fixed-clockv?>E>virt_12m_ckM fixed-clockv?Evirt_13m_ckM fixed-clockv]@?Evirt_19200000_ckM fixed-clockv$?Evirt_26000000_ckM fixed-clockv?Evirt_38_4m_ckM fixed-clockvI?Edpll4_ckMti,omap3-dpll-per-j-type-clock|x D 0?Edpll4_m2_ckMti,divider-clock|?x H?Edpll4_m2x2_mul_ckMfixed-factor-clock|?Edpll4_m2x2_ckMti,hsdiv-gate-clock|Zx ? E omap_96m_alwon_fckMfixed-factor-clock| ?'E'dpll3_ckMti,omap3-dpll-core-clock|x @ 0?Edpll3_m3_ckMti,divider-clock|Zx@?!E!dpll3_m3x2_mul_ckMfixed-factor-clock|!?"E"dpll3_m3x2_ckMti,hsdiv-gate-clock|"Z x ?#E#emu_core_alwon_ckMfixed-factor-clock|#?`E`sys_altclkM fixed-clockv?,E,mcbsp_clksM fixed-clockv?Edpll3_m2_ckMti,divider-clock|Zx @?Ecore_ckMfixed-factor-clock|?$E$dpll1_fckMti,divider-clock|$Zx @?%E%dpll1_ckMti,omap3-dpll-clock|%x  $ @ 4?Edpll1_x2_ckMfixed-factor-clock|?&E&dpll1_x2m2_ckMti,divider-clock|&x D?:E:cm_96m_fckMfixed-factor-clock|'?(E(omap_96m_fckM ti,mux-clock|(Zx @?CECdpll4_m3_ckMti,divider-clock|Z x@?)E)dpll4_m3x2_mul_ckMfixed-factor-clock|)?*E*dpll4_m3x2_ckMti,hsdiv-gate-clock|*Zx ?+E+omap_54m_fckM ti,mux-clock|+,Zx @?6E6cm_96m_d2_fckMfixed-factor-clock|(?-E-omap_48m_fckM ti,mux-clock|-,Zx @?.E.omap_12m_fckMfixed-factor-clock|.?EEEdpll4_m4_ckMti,divider-clock| x@?/E/dpll4_m4x2_mul_ckMti,fixed-factor-clock|/?0E0dpll4_m4x2_ckMti,gate-clock|0Zx ?Edpll4_m5_ckMti,divider-clock|?x@?1E1dpll4_m5x2_mul_ckMti,fixed-factor-clock|1?2E2dpll4_m5x2_ckMti,hsdiv-gate-clock|2Zx ?hEhdpll4_m6_ckMti,divider-clock|Z?x@?3E3dpll4_m6x2_mul_ckMfixed-factor-clock|3?4E4dpll4_m6x2_ckMti,hsdiv-gate-clock|4Zx ?5E5emu_per_alwon_ckMfixed-factor-clock|5?aEaclkout2_src_gate_ckM ti,composite-no-wait-gate-clock|$Zx p?7E7clkout2_src_mux_ckMti,composite-mux-clock|$(6x p?8E8clkout2_src_ckMti,composite-clock|78?9E9sys_clkout2Mti,divider-clock|9Z@x pmpu_ckMfixed-factor-clock|:?;E;arm_fckMti,divider-clock|;x $emu_mpu_alwon_ckMfixed-factor-clock|;?bEbl3_ickMti,divider-clock|$x @?<E<l4_ickMti,divider-clock|<Zx @?=E=rm_ickMti,divider-clock|=Zx @gpt10_gate_fckMti,composite-gate-clock|Z x ??E?gpt10_mux_fckMti,composite-mux-clock|>Zx @?@E@gpt10_fckMti,composite-clock|?@gpt11_gate_fckMti,composite-gate-clock|Z x ?AEAgpt11_mux_fckMti,composite-mux-clock|>Zx @?BEBgpt11_fckMti,composite-clock|ABcore_96m_fckMfixed-factor-clock|C?Emmchs2_fckMti,wait-gate-clock|x Z?Emmchs1_fckMti,wait-gate-clock|x Z?Ei2c3_fckMti,wait-gate-clock|x Z?Ei2c2_fckMti,wait-gate-clock|x Z?Ei2c1_fckMti,wait-gate-clock|x Z?Emcbsp5_gate_fckMti,composite-gate-clock|Z x ?Emcbsp1_gate_fckMti,composite-gate-clock|Z x ?Ecore_48m_fckMfixed-factor-clock|.?DEDmcspi4_fckMti,wait-gate-clock|Dx Z?Emcspi3_fckMti,wait-gate-clock|Dx Z?Emcspi2_fckMti,wait-gate-clock|Dx Z?Emcspi1_fckMti,wait-gate-clock|Dx Z?Euart2_fckMti,wait-gate-clock|Dx Z?Euart1_fckMti,wait-gate-clock|Dx Z ?Ecore_12m_fckMfixed-factor-clock|E?FEFhdq_fckMti,wait-gate-clock|Fx Z?Ecore_l3_ickMfixed-factor-clock|<?GEGsdrc_ickMti,wait-gate-clock|Gx Z?Egpmc_fckMfixed-factor-clock|Gcore_l4_ickMfixed-factor-clock|=?HEHmmchs2_ickMti,omap3-interface-clock|Hx Z?Emmchs1_ickMti,omap3-interface-clock|Hx Z?Ehdq_ickMti,omap3-interface-clock|Hx Z?Emcspi4_ickMti,omap3-interface-clock|Hx Z?Emcspi3_ickMti,omap3-interface-clock|Hx Z?Emcspi2_ickMti,omap3-interface-clock|Hx Z?Emcspi1_ickMti,omap3-interface-clock|Hx Z?Ei2c3_ickMti,omap3-interface-clock|Hx Z?Ei2c2_ickMti,omap3-interface-clock|Hx Z?Ei2c1_ickMti,omap3-interface-clock|Hx Z?Euart2_ickMti,omap3-interface-clock|Hx Z?Euart1_ickMti,omap3-interface-clock|Hx Z ?Egpt11_ickMti,omap3-interface-clock|Hx Z ?Egpt10_ickMti,omap3-interface-clock|Hx Z ?Emcbsp5_ickMti,omap3-interface-clock|Hx Z ?Emcbsp1_ickMti,omap3-interface-clock|Hx Z ?Eomapctrl_ickMti,omap3-interface-clock|Hx Z?Edss_tv_fckMti,gate-clock|6xZ?Edss_96m_fckMti,gate-clock|CxZ?Edss2_alwon_fckMti,gate-clock|xZ?Edummy_ckM fixed-clockvgpt1_gate_fckMti,composite-gate-clock|Zx ?IEIgpt1_mux_fckMti,composite-mux-clock|>x @?JEJgpt1_fckMti,composite-clock|IJaes2_ickMti,omap3-interface-clock|HZx ?Ewkup_32k_fckMfixed-factor-clock|>?KEKgpio1_dbckMti,gate-clock|Kx Z?Esha12_ickMti,omap3-interface-clock|Hx Z?Ewdt2_fckMti,wait-gate-clock|Kx Z?Ewdt2_ickMti,omap3-interface-clock|Lx Z?Ewdt1_ickMti,omap3-interface-clock|Lx Z?Egpio1_ickMti,omap3-interface-clock|Lx Z?Eomap_32ksync_ickMti,omap3-interface-clock|Lx Z?Egpt12_ickMti,omap3-interface-clock|Lx Z?Egpt1_ickMti,omap3-interface-clock|Lx Z?Eper_96m_fckMfixed-factor-clock|'? E per_48m_fckMfixed-factor-clock|.?MEMuart3_fckMti,wait-gate-clock|MxZ ?Egpt2_gate_fckMti,composite-gate-clock|Zx?NENgpt2_mux_fckMti,composite-mux-clock|>x@?OEOgpt2_fckMti,composite-clock|NOgpt3_gate_fckMti,composite-gate-clock|Zx?PEPgpt3_mux_fckMti,composite-mux-clock|>Zx@?QEQgpt3_fckMti,composite-clock|PQgpt4_gate_fckMti,composite-gate-clock|Zx?RERgpt4_mux_fckMti,composite-mux-clock|>Zx@?SESgpt4_fckMti,composite-clock|RSgpt5_gate_fckMti,composite-gate-clock|Zx?TETgpt5_mux_fckMti,composite-mux-clock|>Zx@?UEUgpt5_fckMti,composite-clock|TUgpt6_gate_fckMti,composite-gate-clock|Zx?VEVgpt6_mux_fckMti,composite-mux-clock|>Zx@?WEWgpt6_fckMti,composite-clock|VWgpt7_gate_fckMti,composite-gate-clock|Zx?XEXgpt7_mux_fckMti,composite-mux-clock|>Zx@?YEYgpt7_fckMti,composite-clock|XYgpt8_gate_fckMti,composite-gate-clock|Z x?ZEZgpt8_mux_fckMti,composite-mux-clock|>Zx@?[E[gpt8_fckMti,composite-clock|Z[gpt9_gate_fckMti,composite-gate-clock|Z x?\E\gpt9_mux_fckMti,composite-mux-clock|>Zx@?]E]gpt9_fckMti,composite-clock|\]per_32k_alwon_fckMfixed-factor-clock|>?^E^gpio6_dbckMti,gate-clock|^xZ?Egpio5_dbckMti,gate-clock|^xZ?Egpio4_dbckMti,gate-clock|^xZ?Egpio3_dbckMti,gate-clock|^xZ?Egpio2_dbckMti,gate-clock|^xZ ?Ewdt3_fckMti,wait-gate-clock|^xZ ?Eper_l4_ickMfixed-factor-clock|=?_E_gpio6_ickMti,omap3-interface-clock|_xZ?Egpio5_ickMti,omap3-interface-clock|_xZ?Egpio4_ickMti,omap3-interface-clock|_xZ?Egpio3_ickMti,omap3-interface-clock|_xZ?Egpio2_ickMti,omap3-interface-clock|_xZ ?Ewdt3_ickMti,omap3-interface-clock|_xZ ?Euart3_ickMti,omap3-interface-clock|_xZ ?Euart4_ickMti,omap3-interface-clock|_xZ?Egpt9_ickMti,omap3-interface-clock|_xZ ?Egpt8_ickMti,omap3-interface-clock|_xZ ?Egpt7_ickMti,omap3-interface-clock|_xZ?Egpt6_ickMti,omap3-interface-clock|_xZ?Egpt5_ickMti,omap3-interface-clock|_xZ?Egpt4_ickMti,omap3-interface-clock|_xZ?Egpt3_ickMti,omap3-interface-clock|_xZ?Egpt2_ickMti,omap3-interface-clock|_xZ?Emcbsp2_ickMti,omap3-interface-clock|_xZ?Emcbsp3_ickMti,omap3-interface-clock|_xZ?Emcbsp4_ickMti,omap3-interface-clock|_xZ?Emcbsp2_gate_fckMti,composite-gate-clock|Zx? E mcbsp3_gate_fckMti,composite-gate-clock|Zx? E mcbsp4_gate_fckMti,composite-gate-clock|Zx?Eemu_src_mux_ckM ti,mux-clock|`abx@?cEcemu_src_ckMti,clkdm-gate-clock|c?dEdpclk_fckMti,divider-clock|dZx@pclkx2_fckMti,divider-clock|dZx@atclk_fckMti,divider-clock|dZx@traceclk_src_fckM ti,mux-clock|`abZx@?eEetraceclk_fckMti,divider-clock|eZ x@secure_32k_fckM fixed-clockv?fEfgpt12_fckMfixed-factor-clock|fwdt1_fckMfixed-factor-clock|fsecurity_l4_ick2Mfixed-factor-clock|=?gEgaes1_ickMti,omap3-interface-clock|gZx rng_ickMti,omap3-interface-clock|gx Zsha11_ickMti,omap3-interface-clock|gx Zdes1_ickMti,omap3-interface-clock|gx Zcam_mclkMti,gate-clock|hZxcam_ickM!ti,omap3-no-wait-interface-clock|=xZ?Ecsi2_96m_fckMti,gate-clock|xZ?Esecurity_l3_ickMfixed-factor-clock|<?iEipka_ickMti,omap3-interface-clock|ix Zicr_ickMti,omap3-interface-clock|Hx Zdes2_ickMti,omap3-interface-clock|Hx Zmspro_ickMti,omap3-interface-clock|Hx Zmailboxes_ickMti,omap3-interface-clock|Hx Zssi_l4_ickMfixed-factor-clock|=?pEpsr1_fckMti,wait-gate-clock|x Zsr2_fckMti,wait-gate-clock|x Zsr_l4_ickMfixed-factor-clock|=dpll2_fckMti,divider-clock|$Zx@?jEjdpll2_ckMti,omap3-dpll-clock|jx$@4)1?kEkdpll2_m2_ckMti,divider-clock|kxD?lEliva2_ckMti,wait-gate-clock|lxZ?Emodem_fckMti,omap3-interface-clock|x Z?Esad2d_ickMti,omap3-interface-clock|<x Z?Emad2d_ickMti,omap3-interface-clock|<x Z?Emspro_fckMti,wait-gate-clock|x Zssi_ssr_gate_fck_3430es2M ti,composite-no-wait-gate-clock|Zx ?mEmssi_ssr_div_fck_3430es2Mti,composite-divider-clock|Zx @$E?nEnssi_ssr_fck_3430es2Mti,composite-clock|mn?oEossi_sst_fck_3430es2Mfixed-factor-clock|o?Ehsotgusb_ick_3430es2M"ti,omap3-hsotgusb-interface-clock|Gx Z?Essi_ick_3430es2Mti,omap3-ssi-interface-clock|px Z?Eusim_gate_fckMti,composite-gate-clock|CZ x ?{E{sys_d2_ckMfixed-factor-clock|?rEromap_96m_d2_fckMfixed-factor-clock|C?sEsomap_96m_d4_fckMfixed-factor-clock|C?tEtomap_96m_d8_fckMfixed-factor-clock|C?uEuomap_96m_d10_fckMfixed-factor-clock|C ?vEvdpll5_m2_d4_ckMfixed-factor-clock|q?wEwdpll5_m2_d8_ckMfixed-factor-clock|q?xExdpll5_m2_d16_ckMfixed-factor-clock|q?yEydpll5_m2_d20_ckMfixed-factor-clock|q?zEzusim_mux_fckMti,composite-mux-clock(|rstuvwxyzZx @?|E|usim_fckMti,composite-clock|{|usim_ickMti,omap3-interface-clock|Lx Z ?Edpll5_ckMti,omap3-dpll-clock|x  $ L 4)?}E}dpll5_m2_ckMti,divider-clock|}x P?qEqsgx_gate_fckMti,composite-gate-clock|$Zx ?Ecore_d3_ckMfixed-factor-clock|$?~E~core_d4_ckMfixed-factor-clock|$?Ecore_d6_ckMfixed-factor-clock|$?Eomap_192m_alwon_fckMfixed-factor-clock| ?Ecore_d2_ckMfixed-factor-clock|$?Esgx_mux_fckMti,composite-mux-clock |~(x @?Esgx_fckMti,composite-clock|sgx_ickMti,wait-gate-clock|<x Z?Ecpefuse_fckMti,gate-clock|x Z?Ets_fckMti,gate-clock|>x Z?Eusbtll_fckMti,wait-gate-clock|qx Z?Eusbtll_ickMti,omap3-interface-clock|Hx Z?Emmchs3_ickMti,omap3-interface-clock|Hx Z?Emmchs3_fckMti,wait-gate-clock|x Z?Edss1_alwon_fck_3430es2Mti,dss-gate-clock|Zx?Edss_ick_3430es2Mti,omap3-dss-interface-clock|=xZ?Eusbhost_120m_fckMti,gate-clock|qxZ?Eusbhost_48m_fckMti,dss-gate-clock|.xZ?Eusbhost_ickMti,omap3-dss-interface-clock|=xZ?Euart4_fckMti,wait-gate-clock|MxZ?Eclockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|ddpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|kd2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|}sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH ?Edma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH` Q\ 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ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1 g=>ltxrxdefault #/?mmc@480b4000ti,omap3-hsmmcxH @Vmmc2g/0ltxrxdefault #?Iwlcore@2 ti,wl1835x&mmc@480ad000ti,omap3-hsmmcxH ^mmc3gMNltxrx disabledmmu@480bd400Wti,omap2-iommuxH mmu_ispd?Emmu@5d000000Wti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@tmpu ;< ~commontxrxmcbsp1g ltxrx disabledmcbsp@49022000ti,omap3-mcbspxI I tmpusidetone>?~commontxrxsidetonemcbsp2mcbsp2_sidetoneg!"ltxrxokaydefault ?Emcbsp@49024000ti,omap3-mcbspxI@I tmpusidetoneYZ~commontxrxsidetonemcbsp3mcbsp3_sidetonegltxrx disabledmcbsp@49026000ti,omap3-mcbspxI`tmpu 67 ~commontxrxmcbsp4gltxrx disabledmcbsp@48096000ti,omap3-mcbspxH `tmpu QR ~commontxrxmcbsp5gltxrx disabledsham@480c3000ti,omap3-shamshamxH 0d1gElrxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1timer@49032000ti,omap3430-timerxI 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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslinux,phandle#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatus#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespower#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typeti,modelti,mcbspregulator-always-ongpiosdefault-stategpioenable-active-high