o8()isee,omap3-igep0020ti,omap36xxti,omap3&!7IGEPv2 Rev. C (TI OMAP AM/DM37x)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000d/ocp/serial@49042000memorylmemoryx cpuscpu@0arm,cortex-a8lcpux|cpus 'O 57pmuarm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busxh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busx  pinmux@30 ti,omap3-padconfpinctrl-singlex08+default9pinmux_uart1_pinsCRLW]pinmux_uart3_pinsCnpW]pinmux_mcbsp2_pins C W]pinmux_mmc1_pins0CW]pinmux_mmc2_pins0C(*,.02W]pinmux_smsc9221_pinsCW]pinmux_i2c1_pinsCW]pinmux_i2c3_pinsCW]pinmux_twl4030_pinsCAW]pinmux_tfp410_pinsCW]pinmux_dss_dpi_pinsCW]pinmux_uart2_pins CDFHJW]pinmux_lbee1usjyc_pinsC68:W]scm_conf@270sysconxp0W]clocksmcbsp5_mux_fcketi,composite-mux-clock|rxhW]mcbsp5_fcketi,composite-clock|mcbsp1_mux_fcketi,composite-mux-clock|rxW ] mcbsp1_fcketi,composite-clock| mcbsp2_mux_fcketi,composite-mux-clock| rxW ] mcbsp2_fcketi,composite-clock| mcbsp3_mux_fcketi,composite-mux-clock| xhW]mcbsp3_fcketi,composite-clock|mcbsp4_mux_fcketi,composite-mux-clock| rxhW]mcbsp4_fcketi,composite-clock|clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \pinmux_twl4030_vpins CW]aes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocksvirt_16_8m_cke fixed-clockYW]osc_sys_cke ti,mux-clock|x @W]sys_cketi,divider-clock|rxpW]sys_clkout1eti,gate-clock|x prdpll3_x2_ckefixed-factor-clock|dpll3_m2x2_ckefixed-factor-clock|W]dpll4_x2_ckefixed-factor-clock|corex2_fckefixed-factor-clock|W]wkup_l4_ickefixed-factor-clock|WN]Ncorex2_d3_fckefixed-factor-clock|W]corex2_d5_fckefixed-factor-clock|W]clockdomainscm@48004000 ti,omap3-cmxH@@clocksdummy_apb_pclke fixed-clockomap_32k_fcke fixed-clockW@]@virt_12m_cke fixed-clockW]virt_13m_cke fixed-clock]@W]virt_19200000_cke fixed-clock$W]virt_26000000_cke fixed-clockW]virt_38_4m_cke fixed-clockIW]dpll4_cketi,omap3-dpll-per-j-type-clock|x D 0W]dpll4_m2_cketi,divider-clock|?x HW ] dpll4_m2x2_mul_ckefixed-factor-clock| W!]!dpll4_m2x2_cketi,hsdiv-gate-clock|!rx W"]"omap_96m_alwon_fckefixed-factor-clock|"W)])dpll3_cketi,omap3-dpll-core-clock|x @ 0W]dpll3_m3_cketi,divider-clock|rx@W#]#dpll3_m3x2_mul_ckefixed-factor-clock|#W$]$dpll3_m3x2_cketi,hsdiv-gate-clock|$r x W%]%emu_core_alwon_ckefixed-factor-clock|%Wb]bsys_altclke fixed-clockW.].mcbsp_clkse fixed-clockW]dpll3_m2_cketi,divider-clock|rx @W]core_ckefixed-factor-clock|W&]&dpll1_fcketi,divider-clock|&rx @W']'dpll1_cketi,omap3-dpll-clock|'x  $ @ 4W]dpll1_x2_ckefixed-factor-clock|W(](dpll1_x2m2_cketi,divider-clock|(x DW<]<cm_96m_fckefixed-factor-clock|)W*]*omap_96m_fcke ti,mux-clock|*rx @WE]Edpll4_m3_cketi,divider-clock|r x@W+]+dpll4_m3x2_mul_ckefixed-factor-clock|+W,],dpll4_m3x2_cketi,hsdiv-gate-clock|,rx W-]-omap_54m_fcke ti,mux-clock|-.rx @W8]8cm_96m_d2_fckefixed-factor-clock|*W/]/omap_48m_fcke ti,mux-clock|/.rx @W0]0omap_12m_fckefixed-factor-clock|0WG]Gdpll4_m4_cketi,divider-clock| x@W1]1dpll4_m4x2_mul_cketi,fixed-factor-clock|1W2]2dpll4_m4x2_cketi,gate-clock|2rx W]dpll4_m5_cketi,divider-clock|?x@W3]3dpll4_m5x2_mul_cketi,fixed-factor-clock|3W4]4dpll4_m5x2_cketi,hsdiv-gate-clock|4rx Wj]jdpll4_m6_cketi,divider-clock|r?x@W5]5dpll4_m6x2_mul_ckefixed-factor-clock|5W6]6dpll4_m6x2_cketi,hsdiv-gate-clock|6rx W7]7emu_per_alwon_ckefixed-factor-clock|7Wc]cclkout2_src_gate_cke ti,composite-no-wait-gate-clock|&rx pW9]9clkout2_src_mux_cketi,composite-mux-clock|&*8x pW:]:clkout2_src_cketi,composite-clock|9:W;];sys_clkout2eti,divider-clock|;r@x pmpu_ckefixed-factor-clock|<W=]=arm_fcketi,divider-clock|=x $emu_mpu_alwon_ckefixed-factor-clock|=Wd]dl3_icketi,divider-clock|&x @W>]>l4_icketi,divider-clock|>rx @W?]?rm_icketi,divider-clock|?rx @gpt10_gate_fcketi,composite-gate-clock|r x WA]Agpt10_mux_fcketi,composite-mux-clock|@rx @WB]Bgpt10_fcketi,composite-clock|ABgpt11_gate_fcketi,composite-gate-clock|r x WC]Cgpt11_mux_fcketi,composite-mux-clock|@rx @WD]Dgpt11_fcketi,composite-clock|CDcore_96m_fckefixed-factor-clock|EW]mmchs2_fcketi,wait-gate-clock|x rW]mmchs1_fcketi,wait-gate-clock|x rW]i2c3_fcketi,wait-gate-clock|x rW]i2c2_fcketi,wait-gate-clock|x rW]i2c1_fcketi,wait-gate-clock|x rW]mcbsp5_gate_fcketi,composite-gate-clock|r x W]mcbsp1_gate_fcketi,composite-gate-clock|r x W ] core_48m_fckefixed-factor-clock|0WF]Fmcspi4_fcketi,wait-gate-clock|Fx rW]mcspi3_fcketi,wait-gate-clock|Fx rW]mcspi2_fcketi,wait-gate-clock|Fx rW]mcspi1_fcketi,wait-gate-clock|Fx rW]uart2_fcketi,wait-gate-clock|Fx rW]uart1_fcketi,wait-gate-clock|Fx r W]core_12m_fckefixed-factor-clock|GWH]Hhdq_fcketi,wait-gate-clock|Hx rW]core_l3_ickefixed-factor-clock|>WI]Isdrc_icketi,wait-gate-clock|Ix rW]gpmc_fckefixed-factor-clock|Icore_l4_ickefixed-factor-clock|?WJ]Jmmchs2_icketi,omap3-interface-clock|Jx rW]mmchs1_icketi,omap3-interface-clock|Jx rW]hdq_icketi,omap3-interface-clock|Jx rW]mcspi4_icketi,omap3-interface-clock|Jx rW]mcspi3_icketi,omap3-interface-clock|Jx rW]mcspi2_icketi,omap3-interface-clock|Jx rW]mcspi1_icketi,omap3-interface-clock|Jx rW]i2c3_icketi,omap3-interface-clock|Jx rW]i2c2_icketi,omap3-interface-clock|Jx rW]i2c1_icketi,omap3-interface-clock|Jx rW]uart2_icketi,omap3-interface-clock|Jx rW]uart1_icketi,omap3-interface-clock|Jx r W]gpt11_icketi,omap3-interface-clock|Jx r W]gpt10_icketi,omap3-interface-clock|Jx r W]mcbsp5_icketi,omap3-interface-clock|Jx r W]mcbsp1_icketi,omap3-interface-clock|Jx r W]omapctrl_icketi,omap3-interface-clock|Jx rW]dss_tv_fcketi,gate-clock|8xrW]dss_96m_fcketi,gate-clock|ExrW]dss2_alwon_fcketi,gate-clock|xrW]dummy_cke fixed-clockgpt1_gate_fcketi,composite-gate-clock|rx WK]Kgpt1_mux_fcketi,composite-mux-clock|@x @WL]Lgpt1_fcketi,composite-clock|KLaes2_icketi,omap3-interface-clock|Jrx W]wkup_32k_fckefixed-factor-clock|@WM]Mgpio1_dbcketi,gate-clock|Mx rW]sha12_icketi,omap3-interface-clock|Jx rW]wdt2_fcketi,wait-gate-clock|Mx rW]wdt2_icketi,omap3-interface-clock|Nx rW]wdt1_icketi,omap3-interface-clock|Nx rW]gpio1_icketi,omap3-interface-clock|Nx rW]omap_32ksync_icketi,omap3-interface-clock|Nx rW]gpt12_icketi,omap3-interface-clock|Nx rW]gpt1_icketi,omap3-interface-clock|Nx rW]per_96m_fckefixed-factor-clock|)W ] per_48m_fckefixed-factor-clock|0WO]Ouart3_fcketi,wait-gate-clock|Oxr W]gpt2_gate_fcketi,composite-gate-clock|rxWP]Pgpt2_mux_fcketi,composite-mux-clock|@x@WQ]Qgpt2_fcketi,composite-clock|PQgpt3_gate_fcketi,composite-gate-clock|rxWR]Rgpt3_mux_fcketi,composite-mux-clock|@rx@WS]Sgpt3_fcketi,composite-clock|RSgpt4_gate_fcketi,composite-gate-clock|rxWT]Tgpt4_mux_fcketi,composite-mux-clock|@rx@WU]Ugpt4_fcketi,composite-clock|TUgpt5_gate_fcketi,composite-gate-clock|rxWV]Vgpt5_mux_fcketi,composite-mux-clock|@rx@WW]Wgpt5_fcketi,composite-clock|VWgpt6_gate_fcketi,composite-gate-clock|rxWX]Xgpt6_mux_fcketi,composite-mux-clock|@rx@WY]Ygpt6_fcketi,composite-clock|XYgpt7_gate_fcketi,composite-gate-clock|rxWZ]Zgpt7_mux_fcketi,composite-mux-clock|@rx@W[][gpt7_fcketi,composite-clock|Z[gpt8_gate_fcketi,composite-gate-clock|r xW\]\gpt8_mux_fcketi,composite-mux-clock|@rx@W]]]gpt8_fcketi,composite-clock|\]gpt9_gate_fcketi,composite-gate-clock|r xW^]^gpt9_mux_fcketi,composite-mux-clock|@rx@W_]_gpt9_fcketi,composite-clock|^_per_32k_alwon_fckefixed-factor-clock|@W`]`gpio6_dbcketi,gate-clock|`xrW]gpio5_dbcketi,gate-clock|`xrW]gpio4_dbcketi,gate-clock|`xrW]gpio3_dbcketi,gate-clock|`xrW]gpio2_dbcketi,gate-clock|`xr W]wdt3_fcketi,wait-gate-clock|`xr W]per_l4_ickefixed-factor-clock|?Wa]agpio6_icketi,omap3-interface-clock|axrW]gpio5_icketi,omap3-interface-clock|axrW]gpio4_icketi,omap3-interface-clock|axrW]gpio3_icketi,omap3-interface-clock|axrW]gpio2_icketi,omap3-interface-clock|axr W]wdt3_icketi,omap3-interface-clock|axr W]uart3_icketi,omap3-interface-clock|axr W]uart4_icketi,omap3-interface-clock|axrW]gpt9_icketi,omap3-interface-clock|axr W]gpt8_icketi,omap3-interface-clock|axr W]gpt7_icketi,omap3-interface-clock|axrW]gpt6_icketi,omap3-interface-clock|axrW]gpt5_icketi,omap3-interface-clock|axrW]gpt4_icketi,omap3-interface-clock|axrW]gpt3_icketi,omap3-interface-clock|axrW]gpt2_icketi,omap3-interface-clock|axrW]mcbsp2_icketi,omap3-interface-clock|axrW]mcbsp3_icketi,omap3-interface-clock|axrW]mcbsp4_icketi,omap3-interface-clock|axrW]mcbsp2_gate_fcketi,composite-gate-clock|rxW ] mcbsp3_gate_fcketi,composite-gate-clock|rxW]mcbsp4_gate_fcketi,composite-gate-clock|rxW]emu_src_mux_cke ti,mux-clock|bcdx@We]eemu_src_cketi,clkdm-gate-clock|eWf]fpclk_fcketi,divider-clock|frx@pclkx2_fcketi,divider-clock|frx@atclk_fcketi,divider-clock|frx@traceclk_src_fcke ti,mux-clock|bcdrx@Wg]gtraceclk_fcketi,divider-clock|gr x@secure_32k_fcke fixed-clockWh]hgpt12_fckefixed-factor-clock|hwdt1_fckefixed-factor-clock|hsecurity_l4_ick2efixed-factor-clock|?Wi]iaes1_icketi,omap3-interface-clock|irx rng_icketi,omap3-interface-clock|ix rsha11_icketi,omap3-interface-clock|ix rdes1_icketi,omap3-interface-clock|ix rcam_mclketi,gate-clock|jrxcam_icke!ti,omap3-no-wait-interface-clock|?xrW]csi2_96m_fcketi,gate-clock|xrW]security_l3_ickefixed-factor-clock|>Wk]kpka_icketi,omap3-interface-clock|kx ricr_icketi,omap3-interface-clock|Jx rdes2_icketi,omap3-interface-clock|Jx rmspro_icketi,omap3-interface-clock|Jx rmailboxes_icketi,omap3-interface-clock|Jx rssi_l4_ickefixed-factor-clock|?Wr]rsr1_fcketi,wait-gate-clock|x rsr2_fcketi,wait-gate-clock|x rsr_l4_ickefixed-factor-clock|?dpll2_fcketi,divider-clock|&rx@Wl]ldpll2_cketi,omap3-dpll-clock|lx$@4/AIWm]mdpll2_m2_cketi,divider-clock|mxDWn]niva2_cketi,wait-gate-clock|nxrW]modem_fcketi,omap3-interface-clock|x rW]sad2d_icketi,omap3-interface-clock|>x rW]mad2d_icketi,omap3-interface-clock|>x rW]mspro_fcketi,wait-gate-clock|x rssi_ssr_gate_fck_3430es2e ti,composite-no-wait-gate-clock|rx Wo]ossi_ssr_div_fck_3430es2eti,composite-divider-clock|rx @$]Wp]pssi_ssr_fck_3430es2eti,composite-clock|opWq]qssi_sst_fck_3430es2efixed-factor-clock|qW]hsotgusb_ick_3430es2e"ti,omap3-hsotgusb-interface-clock|Ix rW]ssi_ick_3430es2eti,omap3-ssi-interface-clock|rx rW]usim_gate_fcketi,composite-gate-clock|Er x W}]}sys_d2_ckefixed-factor-clock|Wt]tomap_96m_d2_fckefixed-factor-clock|EWu]uomap_96m_d4_fckefixed-factor-clock|EWv]vomap_96m_d8_fckefixed-factor-clock|EWw]womap_96m_d10_fckefixed-factor-clock|E Wx]xdpll5_m2_d4_ckefixed-factor-clock|sWy]ydpll5_m2_d8_ckefixed-factor-clock|sWz]zdpll5_m2_d16_ckefixed-factor-clock|sW{]{dpll5_m2_d20_ckefixed-factor-clock|sW|]|usim_mux_fcketi,composite-mux-clock(|tuvwxyz{|rx @W~]~usim_fcketi,composite-clock|}~usim_icketi,omap3-interface-clock|Nx r W]dpll5_cketi,omap3-dpll-clock|x  $ L 4/AW]dpll5_m2_cketi,divider-clock|x PWs]ssgx_gate_fcketi,composite-gate-clock|&rx W]core_d3_ckefixed-factor-clock|&W]core_d4_ckefixed-factor-clock|&W]core_d6_ckefixed-factor-clock|&W]omap_192m_alwon_fckefixed-factor-clock|"W]core_d2_ckefixed-factor-clock|&W]sgx_mux_fcketi,composite-mux-clock |*x @W]sgx_fcketi,composite-clock|sgx_icketi,wait-gate-clock|>x rW]cpefuse_fcketi,gate-clock|x rW]ts_fcketi,gate-clock|@x rW]usbtll_fcketi,wait-gate-clock|sx rW]usbtll_icketi,omap3-interface-clock|Jx rW]mmchs3_icketi,omap3-interface-clock|Jx rW]mmchs3_fcketi,wait-gate-clock|x rW]dss1_alwon_fck_3430es2eti,dss-gate-clock|rxW]dss_ick_3430es2eti,omap3-dss-interface-clock|?xrW]usbhost_120m_fcketi,gate-clock|sxrW]usbhost_48m_fcketi,dss-gate-clock|0xrW]usbhost_icketi,omap3-dss-interface-clock|?xrW]uart4_fcketi,wait-gate-clock|OxrW]clockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|fdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|md2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH W]dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH` it `W]pbias_regulatorti,pbias-omapxpbias_mmc_omap2430pbias_mmc_omap2430w@-W]gpio@48310000ti,omap3-gpioxH1gpio1W]gpio@49050000ti,omap3-gpioxIgpio2gpio@49052000ti,omap3-gpioxI gpio3gpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5W ] gpio@49058000ti,omap3-gpioxI"gpio6W]serial@4806a000ti,omap3-uartxH H12txrxuart1l+default9serial@4806c000ti,omap3-uartxHI34txrxuart2l+default9serial@49020000ti,omap3-uartxIJ56txrxuart3l+default9i2c@48070000 ti,omap3-i2cxH8txrxi2c1+default9'@twl@48xH& ti,twl4030+default9audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0W]regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5W]regulator-vusb1v8ti,twl4030-vusb1v8W]regulator-vusb3v1ti,twl4030-vusb3v1W]regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@ vdds_dsiregulator-vsimti,twl4030-vsimw@-W]gpioti,twl4030-gpio$W]twl4030-usbti,twl4030-usb 0>LZcW]pwmti,twl4030-pwmnpwmledti,twl4030-pwmlednpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadymadcti,twl4030-madci2c@48072000 ti,omap3-i2cxH 9txrxi2c2i2c@48060000 ti,omap3-i2cxH=txrxi2c3+default9W ] eeprom@50 ti,eepromxPmailbox@48094000ti,omap3-mailboxmailboxxH @dsp  spi@48098000ti,omap2-mcspixH Amcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH Bmcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0mcspi4FGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1=>txrx+default9(8mmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx+default9(8Bmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx Pdisabledmmu@480bd400Wti,omap2-iommuxH mmu_ispdW]mmu@5d000000Wti,omap2-iommux]mmu_iva Pdisabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@tmpu ;< ~commontxrxmcbsp1 txrx Pdisabledmcbsp@49022000ti,omap3-mcbspxI I tmpusidetone>?~commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxPokay+default9W]mcbsp@49024000ti,omap3-mcbspxI@I tmpusidetoneYZ~commontxrxsidetonemcbsp3mcbsp3_sidetonetxrx Pdisabledmcbsp@49026000ti,omap3-mcbspxI`tmpu 67 ~commontxrxmcbsp4txrx Pdisabledmcbsp@48096000ti,omap3-mcbspxH `tmpu QR ~commontxrxmcbsp5txrx Pdisabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1timer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer5timer@4903a000ti,omap3430-timerxI*timer6timer@4903c000ti,omap3430-timerxI+timer7timer@4903e000ti,omap3430-timerxI,timer8timer@49040000ti,omap3430-timerxI-timer9timer@48086000ti,omap3430-timerxH`.timer10timer@48088000ti,omap3430-timerxH/timer11timer@48304000ti,omap3430-timerxH0@_timer12usbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hs ehci-phyohci@48064400ti,ohci-omap3xHD&Lehci@48064800 ti,ehci-omapxHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcxn ,nand@0,0micron,mt29c4g96maz x"4bch8DUc,u,",(6@RR (partition@05SPLxpartition@800005U-Bootxpartition@1c0000 5Environmentx(partition@2800005Kernelx80partition@780000 5Filesystemxhethernet@gpmcsmsc,lan9221smsc,lan9115;FUc*u$  X*f$<6$t *+default9 x&usb_otg_hs@480ab000ti,omap3-musbxH \]~mcdma usb_otg_hs4?G P_ gusb2-phy^q2dss@48050000 ti,omap3-dssxHPok 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%offuser25omap3:green:user1 hsusb1_power_regregulator-fixed hsusb1_vbus2Z2Z 38pW]hsusb1_phyusb-nop-xceiv IUW]encoder@0 ti,tfp410 ` portsport@0xendpoint@0wW]port@1xendpoint@0w W ] connector@0dvi-connector5dvipx portendpointw W ] lbee1usjyc_pdnregulator-fixedregulator-lbee1usjyc-pdn2Z2Z 3 8'W]lbee1usjyc_reset_n_wregulator-fixedregulator-lbee1usjyc-reset-n-w2Z2Z 3 W] #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandle#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removablestatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modephysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-lines#address-cellti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-typeti,modelti,mcbspregulator-always-ongpiosdefault-stategpiostartup-delay-usreset-gpiosvcc-supplypowerdown-gpiosdigitalddc-i2c-busenable-active-high