8(ti,omap3-evmti,omap3&7TI OMAP35XX EVM (TMDSEVM3530)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/displaymemorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busyh l3_mainl4@48000000ti,omap3-l4-coresimple-bus Hscm@2000ti,omap3-scmsimple-busy  pinmux@30 ti,omap3-padconfpinctrl-singley088>pinmux_twl4030_pinsFA8>scm_conf@270sysconyp08>clocksmcbsp5_mux_fckZti,composite-mux-clock}gyh8>mcbsp5_fckZti,composite-clock}mcbsp1_mux_fckZti,composite-mux-clock}gy8 > mcbsp1_fckZti,composite-clock} mcbsp2_mux_fckZti,composite-mux-clock} gy8 > mcbsp2_fckZti,composite-clock} mcbsp3_mux_fckZti,composite-mux-clock} yh8>mcbsp3_fckZti,composite-clock} mcbsp4_mux_fckZti,composite-mux-clock} gyh8>mcbsp4_fckZti,composite-clock}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \pinmux_twl4030_vpins F8>aes@480c5000 ti,omap3-aesaesyH PPtABytxrxprm@48306000 ti,omap3-prmyH0`@ clocksvirt_16_8m_ckZ fixed-clockY8>osc_sys_ckZ ti,mux-clock}y @8>sys_ckZti,divider-clock}gyp8>sys_clkout1Zti,gate-clock}y pgdpll3_x2_ckZfixed-factor-clock}dpll3_m2x2_ckZfixed-factor-clock}8>dpll4_x2_ckZfixed-factor-clock}corex2_fckZfixed-factor-clock}8>wkup_l4_ickZfixed-factor-clock}8M>Mcorex2_d3_fckZfixed-factor-clock}8>corex2_d5_fckZfixed-factor-clock}8>clockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclkZ fixed-clockomap_32k_fckZ fixed-clock8?>?virt_12m_ckZ fixed-clock8>virt_13m_ckZ fixed-clock]@8>virt_19200000_ckZ fixed-clock$8>virt_26000000_ckZ fixed-clock8>virt_38_4m_ckZ fixed-clockI8>dpll4_ckZti,omap3-dpll-per-clock}y D 08>dpll4_m2_ckZti,divider-clock}?y H8>dpll4_m2x2_mul_ckZfixed-factor-clock}8 > dpll4_m2x2_ckZti,gate-clock} gy 8!>!omap_96m_alwon_fckZfixed-factor-clock}!8(>(dpll3_ckZti,omap3-dpll-core-clock}y @ 08>dpll3_m3_ckZti,divider-clock}gy@8">"dpll3_m3x2_mul_ckZfixed-factor-clock}"8#>#dpll3_m3x2_ckZti,gate-clock}#g y 8$>$emu_core_alwon_ckZfixed-factor-clock}$8a>asys_altclkZ fixed-clock8->-mcbsp_clksZ fixed-clock8>dpll3_m2_ckZti,divider-clock}gy @8>core_ckZfixed-factor-clock}8%>%dpll1_fckZti,divider-clock}%gy @8&>&dpll1_ckZti,omap3-dpll-clock}&y  $ @ 48>dpll1_x2_ckZfixed-factor-clock}8'>'dpll1_x2m2_ckZti,divider-clock}'y D8;>;cm_96m_fckZfixed-factor-clock}(8)>)omap_96m_fckZ ti,mux-clock})gy @8D>Ddpll4_m3_ckZti,divider-clock}g y@8*>*dpll4_m3x2_mul_ckZfixed-factor-clock}*8+>+dpll4_m3x2_ckZti,gate-clock}+gy 8,>,omap_54m_fckZ ti,mux-clock},-gy @87>7cm_96m_d2_fckZfixed-factor-clock})8.>.omap_48m_fckZ ti,mux-clock}.-gy @8/>/omap_12m_fckZfixed-factor-clock}/8F>Fdpll4_m4_ckZti,divider-clock} y@80>0dpll4_m4x2_mul_ckZti,fixed-factor-clock}081>1dpll4_m4x2_ckZti,gate-clock}1gy 8>dpll4_m5_ckZti,divider-clock}?y@82>2dpll4_m5x2_mul_ckZti,fixed-factor-clock}283>3dpll4_m5x2_ckZti,gate-clock}3gy 8i>idpll4_m6_ckZti,divider-clock}g?y@84>4dpll4_m6x2_mul_ckZfixed-factor-clock}485>5dpll4_m6x2_ckZti,gate-clock}5gy 86>6emu_per_alwon_ckZfixed-factor-clock}68b>bclkout2_src_gate_ckZ ti,composite-no-wait-gate-clock}%gy p88>8clkout2_src_mux_ckZti,composite-mux-clock}%)7y p89>9clkout2_src_ckZti,composite-clock}898:>:sys_clkout2Zti,divider-clock}:g@y pmpu_ckZfixed-factor-clock};8<><arm_fckZti,divider-clock}<y $emu_mpu_alwon_ckZfixed-factor-clock}<8c>cl3_ickZti,divider-clock}%y @8=>=l4_ickZti,divider-clock}=gy @8>>>rm_ickZti,divider-clock}>gy @gpt10_gate_fckZti,composite-gate-clock}g y 8@>@gpt10_mux_fckZti,composite-mux-clock}?gy @8A>Agpt10_fckZti,composite-clock}@Agpt11_gate_fckZti,composite-gate-clock}g y 8B>Bgpt11_mux_fckZti,composite-mux-clock}?gy @8C>Cgpt11_fckZti,composite-clock}BCcore_96m_fckZfixed-factor-clock}D8>mmchs2_fckZti,wait-gate-clock}y g8>mmchs1_fckZti,wait-gate-clock}y g8>i2c3_fckZti,wait-gate-clock}y g8>i2c2_fckZti,wait-gate-clock}y g8>i2c1_fckZti,wait-gate-clock}y g8>mcbsp5_gate_fckZti,composite-gate-clock}g y 8>mcbsp1_gate_fckZti,composite-gate-clock}g y 8>core_48m_fckZfixed-factor-clock}/8E>Emcspi4_fckZti,wait-gate-clock}Ey g8>mcspi3_fckZti,wait-gate-clock}Ey g8>mcspi2_fckZti,wait-gate-clock}Ey g8>mcspi1_fckZti,wait-gate-clock}Ey g8>uart2_fckZti,wait-gate-clock}Ey g8>uart1_fckZti,wait-gate-clock}Ey g 8>core_12m_fckZfixed-factor-clock}F8G>Ghdq_fckZti,wait-gate-clock}Gy g8>core_l3_ickZfixed-factor-clock}=8H>Hsdrc_ickZti,wait-gate-clock}Hy g8>gpmc_fckZfixed-factor-clock}Hcore_l4_ickZfixed-factor-clock}>8I>Immchs2_ickZti,omap3-interface-clock}Iy g8>mmchs1_ickZti,omap3-interface-clock}Iy g8>hdq_ickZti,omap3-interface-clock}Iy g8>mcspi4_ickZti,omap3-interface-clock}Iy g8>mcspi3_ickZti,omap3-interface-clock}Iy g8>mcspi2_ickZti,omap3-interface-clock}Iy g8>mcspi1_ickZti,omap3-interface-clock}Iy g8>i2c3_ickZti,omap3-interface-clock}Iy g8>i2c2_ickZti,omap3-interface-clock}Iy g8>i2c1_ickZti,omap3-interface-clock}Iy g8>uart2_ickZti,omap3-interface-clock}Iy g8>uart1_ickZti,omap3-interface-clock}Iy g 8>gpt11_ickZti,omap3-interface-clock}Iy g 8>gpt10_ickZti,omap3-interface-clock}Iy g 8>mcbsp5_ickZti,omap3-interface-clock}Iy g 8>mcbsp1_ickZti,omap3-interface-clock}Iy g 8>omapctrl_ickZti,omap3-interface-clock}Iy g8>dss_tv_fckZti,gate-clock}7yg8>dss_96m_fckZti,gate-clock}Dyg8>dss2_alwon_fckZti,gate-clock}yg8>dummy_ckZ fixed-clockgpt1_gate_fckZti,composite-gate-clock}gy 8J>Jgpt1_mux_fckZti,composite-mux-clock}?y @8K>Kgpt1_fckZti,composite-clock}JKaes2_ickZti,omap3-interface-clock}Igy 8>wkup_32k_fckZfixed-factor-clock}?8L>Lgpio1_dbckZti,gate-clock}Ly g8>sha12_ickZti,omap3-interface-clock}Iy g8>wdt2_fckZti,wait-gate-clock}Ly g8>wdt2_ickZti,omap3-interface-clock}My g8>wdt1_ickZti,omap3-interface-clock}My g8>gpio1_ickZti,omap3-interface-clock}My g8>omap_32ksync_ickZti,omap3-interface-clock}My g8>gpt12_ickZti,omap3-interface-clock}My g8>gpt1_ickZti,omap3-interface-clock}My g8>per_96m_fckZfixed-factor-clock}(8 > per_48m_fckZfixed-factor-clock}/8N>Nuart3_fckZti,wait-gate-clock}Nyg 8>gpt2_gate_fckZti,composite-gate-clock}gy8O>Ogpt2_mux_fckZti,composite-mux-clock}?y@8P>Pgpt2_fckZti,composite-clock}OPgpt3_gate_fckZti,composite-gate-clock}gy8Q>Qgpt3_mux_fckZti,composite-mux-clock}?gy@8R>Rgpt3_fckZti,composite-clock}QRgpt4_gate_fckZti,composite-gate-clock}gy8S>Sgpt4_mux_fckZti,composite-mux-clock}?gy@8T>Tgpt4_fckZti,composite-clock}STgpt5_gate_fckZti,composite-gate-clock}gy8U>Ugpt5_mux_fckZti,composite-mux-clock}?gy@8V>Vgpt5_fckZti,composite-clock}UVgpt6_gate_fckZti,composite-gate-clock}gy8W>Wgpt6_mux_fckZti,composite-mux-clock}?gy@8X>Xgpt6_fckZti,composite-clock}WXgpt7_gate_fckZti,composite-gate-clock}gy8Y>Ygpt7_mux_fckZti,composite-mux-clock}?gy@8Z>Zgpt7_fckZti,composite-clock}YZgpt8_gate_fckZti,composite-gate-clock}g y8[>[gpt8_mux_fckZti,composite-mux-clock}?gy@8\>\gpt8_fckZti,composite-clock}[\gpt9_gate_fckZti,composite-gate-clock}g y8]>]gpt9_mux_fckZti,composite-mux-clock}?gy@8^>^gpt9_fckZti,composite-clock}]^per_32k_alwon_fckZfixed-factor-clock}?8_>_gpio6_dbckZti,gate-clock}_yg8>gpio5_dbckZti,gate-clock}_yg8>gpio4_dbckZti,gate-clock}_yg8>gpio3_dbckZti,gate-clock}_yg8>gpio2_dbckZti,gate-clock}_yg 8>wdt3_fckZti,wait-gate-clock}_yg 8>per_l4_ickZfixed-factor-clock}>8`>`gpio6_ickZti,omap3-interface-clock}`yg8>gpio5_ickZti,omap3-interface-clock}`yg8>gpio4_ickZti,omap3-interface-clock}`yg8>gpio3_ickZti,omap3-interface-clock}`yg8>gpio2_ickZti,omap3-interface-clock}`yg 8>wdt3_ickZti,omap3-interface-clock}`yg 8>uart3_ickZti,omap3-interface-clock}`yg 8>uart4_ickZti,omap3-interface-clock}`yg8>gpt9_ickZti,omap3-interface-clock}`yg 8>gpt8_ickZti,omap3-interface-clock}`yg 8>gpt7_ickZti,omap3-interface-clock}`yg8>gpt6_ickZti,omap3-interface-clock}`yg8>gpt5_ickZti,omap3-interface-clock}`yg8>gpt4_ickZti,omap3-interface-clock}`yg8>gpt3_ickZti,omap3-interface-clock}`yg8>gpt2_ickZti,omap3-interface-clock}`yg8>mcbsp2_ickZti,omap3-interface-clock}`yg8>mcbsp3_ickZti,omap3-interface-clock}`yg8>mcbsp4_ickZti,omap3-interface-clock}`yg8>mcbsp2_gate_fckZti,composite-gate-clock}gy8 > mcbsp3_gate_fckZti,composite-gate-clock}gy8 > mcbsp4_gate_fckZti,composite-gate-clock}gy8>emu_src_mux_ckZ ti,mux-clock}abcy@8d>demu_src_ckZti,clkdm-gate-clock}d8e>epclk_fckZti,divider-clock}egy@pclkx2_fckZti,divider-clock}egy@atclk_fckZti,divider-clock}egy@traceclk_src_fckZ ti,mux-clock}abcgy@8f>ftraceclk_fckZti,divider-clock}fg y@secure_32k_fckZ fixed-clock8g>ggpt12_fckZfixed-factor-clock}gwdt1_fckZfixed-factor-clock}gsecurity_l4_ick2Zfixed-factor-clock}>8h>haes1_ickZti,omap3-interface-clock}hgy rng_ickZti,omap3-interface-clock}hy gsha11_ickZti,omap3-interface-clock}hy gdes1_ickZti,omap3-interface-clock}hy gcam_mclkZti,gate-clock}igycam_ickZ!ti,omap3-no-wait-interface-clock}>yg8>csi2_96m_fckZti,gate-clock}yg8>security_l3_ickZfixed-factor-clock}=8j>jpka_ickZti,omap3-interface-clock}jy gicr_ickZti,omap3-interface-clock}Iy gdes2_ickZti,omap3-interface-clock}Iy gmspro_ickZti,omap3-interface-clock}Iy gmailboxes_ickZti,omap3-interface-clock}Iy gssi_l4_ickZfixed-factor-clock}>8q>qsr1_fckZti,wait-gate-clock}y gsr2_fckZti,wait-gate-clock}y gsr_l4_ickZfixed-factor-clock}>dpll2_fckZti,divider-clock}%gy@8k>kdpll2_ckZti,omap3-dpll-clock}ky$@4$6>8l>ldpll2_m2_ckZti,divider-clock}lyD8m>miva2_ckZti,wait-gate-clock}myg8>modem_fckZti,omap3-interface-clock}y g8>sad2d_ickZti,omap3-interface-clock}=y g8>mad2d_ickZti,omap3-interface-clock}=y g8>mspro_fckZti,wait-gate-clock}y gssi_ssr_gate_fck_3430es2Z ti,composite-no-wait-gate-clock}gy 8n>nssi_ssr_div_fck_3430es2Zti,composite-divider-clock}gy @$R8o>ossi_ssr_fck_3430es2Zti,composite-clock}no8p>pssi_sst_fck_3430es2Zfixed-factor-clock}p8>hsotgusb_ick_3430es2Z"ti,omap3-hsotgusb-interface-clock}Hy g8>ssi_ick_3430es2Zti,omap3-ssi-interface-clock}qy g8>usim_gate_fckZti,composite-gate-clock}Dg y 8|>|sys_d2_ckZfixed-factor-clock}8s>somap_96m_d2_fckZfixed-factor-clock}D8t>tomap_96m_d4_fckZfixed-factor-clock}D8u>uomap_96m_d8_fckZfixed-factor-clock}D8v>vomap_96m_d10_fckZfixed-factor-clock}D 8w>wdpll5_m2_d4_ckZfixed-factor-clock}r8x>xdpll5_m2_d8_ckZfixed-factor-clock}r8y>ydpll5_m2_d16_ckZfixed-factor-clock}r8z>zdpll5_m2_d20_ckZfixed-factor-clock}r8{>{usim_mux_fckZti,composite-mux-clock(}stuvwxyz{gy @8}>}usim_fckZti,composite-clock}|}usim_ickZti,omap3-interface-clock}My g 8>dpll5_ckZti,omap3-dpll-clock}y  $ L 4$68~>~dpll5_m2_ckZti,divider-clock}~y P8r>rsgx_gate_fckZti,composite-gate-clock}%gy 8>core_d3_ckZfixed-factor-clock}%8>core_d4_ckZfixed-factor-clock}%8>core_d6_ckZfixed-factor-clock}%8>omap_192m_alwon_fckZfixed-factor-clock}!8>core_d2_ckZfixed-factor-clock}%8>sgx_mux_fckZti,composite-mux-clock })y @8>sgx_fckZti,composite-clock}sgx_ickZti,wait-gate-clock}=y g8>cpefuse_fckZti,gate-clock}y g8>ts_fckZti,gate-clock}?y g8>usbtll_fckZti,wait-gate-clock}ry g8>usbtll_ickZti,omap3-interface-clock}Iy g8>mmchs3_ickZti,omap3-interface-clock}Iy g8>mmchs3_fckZti,wait-gate-clock}y g8>dss1_alwon_fck_3430es2Zti,dss-gate-clock}gy8>dss_ick_3430es2Zti,omap3-dss-interface-clock}>yg8>usbhost_120m_fckZti,gate-clock}ryg8>usbhost_48m_fckZti,dss-gate-clock}/yg8>usbhost_ickZti,omap3-dss-interface-clock}>yg8>clockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}edpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}ld2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}~sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH 8>dma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH` ^i v`8>pbias_regulatorti,pbias-omapypbias_mmc_omap2430pbias_mmc_omap2430w@-8>gpio@48310000ti,omap3-gpioyH1gpio18>gpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI 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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pins#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requestssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xylinux,wakeuppendown-gpioti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesstatusreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerremote-endpointdata-linesiommusti,phy-typelabelgpioslinux,default-triggerstartup-delay-usenable-active-highvin-supplydefault-onenable-active-lowpower-supplyenable-gpiosreset-gpiosmode-gpios