8v(vvscom,onriscti,am33xx&7OnRISC Baltos iR 5221chosenaliases=/ocp/i2c@44e0b000B/ocp/i2c@4802a000G/ocp/i2c@4819c000L/ocp/serial@44e09000T/ocp/serial@48022000\/ocp/serial@48024000d/ocp/serial@481a6000l/ocp/serial@481a8000t/ocp/serial@481aa000|/ocp/can@481cc000/ocp/can@481d0000/ocp/usb@47400000/usb@47401000/ocp/usb@47400000/usb@47401800#/ocp/usb@47400000/usb-phy@47401300#/ocp/usb@47400000/usb-phy@47401b00&/ocp/ethernet@4a100000/slave@4a100200&/ocp/ethernet@4a100000/slave@4a100300memorymemorycpuscpu@0arm,cortex-a8cpu  '( *28*cpupmuarm,cortex-a8-pmusocti,omap-inframpu ti,omap3-mpumpuocp simple-bus'l3_mainl4_wkup@44c00000ti,am3-l4-wkupsimple-bus 'D(prcm@200000 ti,am3-prcm @clocksclk_32768_ck. fixed-clock;KQclk_rc32k_ck. fixed-clock;}KQvirt_19200000_ck. fixed-clock;$K Q virt_24000000_ck. fixed-clock;n6K!Q!virt_25000000_ck. fixed-clock;}x@K"Q"virt_26000000_ck. fixed-clock;K#Q#tclkin_ck. fixed-clock;KQdpll_core_ck.ti,am3-dpll-core-clock \hKQdpll_core_x2_ck.ti,am3-dpll-x2-clockKQdpll_core_m4_ck.ti,divider-clockYdKQdpll_core_m5_ck.ti,divider-clockYdKQdpll_core_m6_ck.ti,divider-clockYddpll_mpu_ck.ti,am3-dpll-clock  ,KQdpll_mpu_m2_ck.ti,divider-clockYddpll_ddr_ck.ti,am3-dpll-no-gate-clock 4@KQdpll_ddr_m2_ck.ti,divider-clockYdKQdpll_ddr_m2_div2_ck.fixed-factor-clock{dpll_disp_ck.ti,am3-dpll-no-gate-clock HTK Q dpll_disp_m2_ck.ti,divider-clock YdKQdpll_per_ck.!ti,am3-dpll-no-gate-j-type-clock pK Q dpll_per_m2_ck.ti,divider-clock YdK Q dpll_per_m2_div4_wkupdm_ck.fixed-factor-clock {dpll_per_m2_div4_ck.fixed-factor-clock {cefuse_fck.ti,gate-clock clk_24mhz.fixed-factor-clock {K Q clkdiv32k_ck.fixed-factor-clock {K Q clkdiv32k_ick.ti,gate-clock LKQl3_gclk.fixed-factor-clock{KQpruss_ocp_gclk. ti,mux-clock0mmu_fck.ti,gate-clock timer1_fck. ti,mux-clock(timer2_fck. ti,mux-clock timer3_fck. ti,mux-clock  timer4_fck. ti,mux-clock timer5_fck. ti,mux-clock timer6_fck. ti,mux-clock timer7_fck. ti,mux-clock usbotg_fck.ti,gate-clock |dpll_core_m4_div2_ck.fixed-factor-clock{KQieee5000_fck.ti,gate-clockwdt1_fck. ti,mux-clock8l4_rtc_gclk.fixed-factor-clock{l4hs_gclk.fixed-factor-clock{l3s_gclk.fixed-factor-clock{l4fw_gclk.fixed-factor-clock{l4ls_gclk.fixed-factor-clock{K$Q$sysclk_div_ck.fixed-factor-clock{cpsw_125mhz_gclk.fixed-factor-clock{K<Q<cpsw_cpts_rft_clk. ti,mux-clock K=Q=gpio0_dbclk_mux_ck. ti,mux-clock <KQgpio0_dbclk.ti,gate-clockgpio1_dbclk.ti,gate-clockgpio2_dbclk.ti,gate-clockgpio3_dbclk.ti,gate-clocklcd_gclk. ti,mux-clock  4KQmmc_clk.fixed-factor-clock {gfx_fclk_clksel_ck. ti,mux-clock ,KQgfx_fck_div_ck.ti,divider-clock,Ysysclkout_pre_ck. ti,mux-clock KQclkout2_div_ck.ti,divider-clockYKQdbg_sysclk_ck.ti,gate-clockKQdbg_clka_ck.ti,gate-clockKQstm_pmd_clock_mux_ck. ti,mux-clockKQtrace_pmd_clk_mux_ck. ti,mux-clockKQstm_clk_div_ck.ti,divider-clockY@trace_clk_div_ck.ti,divider-clockY@clkout2_ck.ti,gate-clockclockdomainsclk_24mhz_clkdmti,clockdomainscm@210000ti,am3-scmsimple-bus!  '! pinmux@800pinctrl-single8 pinmux_mmc2_pins8 2$2(2,2227K3Q3pinmux_wl12xx_gpioKEQEpinmux_tps65910_pinsx7K.Q.pinmux_tca6416_pins7K0Q0pinmux_i2c1_pinsX*\*K-Q-pinmux_dcan1_pinsh l*K7Q7pinmux_uart0_pinsp0tK&Q&pinmux_uart1_pins@((x'|'''K'Q'pinmux_uart2_pinsHP)T '04'8'<'7K*Q*cpsw_default !$(<!@!D @D"HLPTX\"`"d"h"l"K>Q>cpsw_sleep ''$'('<'@'D'@'D'H'L'P'T'X'\'`'d'h'l'K?Q?davinci_mdio_defaultH0LK@Q@davinci_mdio_sleepH'L'KAQAnandflash_pins_s0x000 00000p0t7|KCQCscm_conf@0sysconK5Q5clockssys_clkin_ck. ti,mux-clock !"#@KQadc_tsc_fck.fixed-factor-clock{dcan0_fck.fixed-factor-clock{K4Q4dcan1_fck.fixed-factor-clock{K6Q6mcasp0_fck.fixed-factor-clock{mcasp1_fck.fixed-factor-clock{smartreflex0_fck.fixed-factor-clock{smartreflex1_fck.fixed-factor-clock{sha0_fck.fixed-factor-clock{aes0_fck.fixed-factor-clock{rng_fck.fixed-factor-clock{ehrpwm0_tbclk@44e10664.ti,gate-clock$dehrpwm1_tbclk@44e10664.ti,gate-clock$dehrpwm2_tbclk@44e10664.ti,gate-clock$dclockdomainsinterrupt-controller@48200000ti,am33xx-intc*H KQedma@49000000 ti,edma3tpcctptc0tptc1tptc2ID@  ;K%Q%gpio@44e07000ti,omap4-gpiogpio1FV*Dp`bK)Q)gpio@4804c000ti,omap4-gpiogpio2FV*HbK+Q+gpio@481ac000ti,omap4-gpiogpio3FV*H K(Q(gpio@481ae000ti,omap4-gpiogpio4FV*H>K,Q,serial@44e09000ti,omap3-uartuart1;lD Hvokay}%%txrxdefault&serial@48022000ti,omap3-uartuart2;lH Ivokay}%%txrxdefault' ( ( ( ( )  ) serial@48024000ti,omap3-uartuart3;lH@ Jvokay}%%txrxdefault* +  +  + + , ,serial@481a6000ti,omap3-uartuart4;lH` , vdisabledserial@481a8000ti,omap3-uartuart5;lH - vdisabledserial@481aa000ti,omap3-uartuart6;lH . vdisabledi2c@44e0b000 ti,omap4-i2ci2c1DF vdisabledi2c@4802a000 ti,omap4-i2ci2c2HGvokaydefault-;tps@2d-FV&+default. ti,tps65910//////(/4/Aregulatorsregulator@0Rvrtcgregulator@1Rviogregulator@2Rvdd1{vdd_mpu tgKQregulator@3Rvdd2 {vdd_core t0gregulator@4Rvdd3gregulator@5Rvdig1gregulator@6Rvdig2gregulator@7Rvpllgregulator@8Rvdacgregulator@9 Rvaux1gregulator@10 Rvaux2gregulator@11 Rvaux33gregulator@12 Rvmmcw@2ZgK1Q1regulator@13 Rvbbat24@50 at24,24c02Pgpio@20 ti,tca6416 FV&)default0i2c@4819c000 ti,omap4-i2ci2c3H vdisabledmmc@48060000ti,omap4-hsmmcmmc1}%%txrx@&Hvokay1mmc@481d8000ti,omap4-hsmmcmmc2}%%txrx&Hvokay2"3=default3wlcore@2 ti,wl1835&,mmc@47810000ti,omap4-hsmmcmmc3&G vdisabledspinlock@480ca000ti,omap4-hwspinlockH  spinlockPwdt@44e35000 ti,omap3-wdt wd_timer2DP[can@481cc000ti,am3352-d_cand_can0H 4fck ^5D4 vdisabledcan@481d0000ti,am3352-d_cand_can1H 6fck ^5D7vokaydefault7mailbox@480C8000ti,omap4-mailboxH Mmailboxmywkup_m3  timer@44e31000ti,am335x-timer-1msDCtimer1timer@48040000ti,am335x-timerHDtimer2timer@48042000ti,am335x-timerH Etimer3timer@48044000ti,am335x-timerH@\timer4timer@48046000ti,am335x-timerH`]timer5timer@48048000ti,am335x-timerH^timer6timer@4804a000ti,am335x-timerH_timer7rtc@44e3e000ti,am3352-rtcti,da830-rtcDKLrtcspi@48030000ti,omap4-mcspiHAspi0 }%%%%tx0rx0tx1rx1 vdisabledspi@481a0000ti,omap4-mcspiH}spi1 }%*%+%,%-tx0rx0tx1rx1 vdisabledusb@47400000ti,am33xx-usbG@' usb_otg_hsvokaycontrol@44e10620ti,am335x-usb-ctrl-moduleD DHphy_ctrlwakeupvokayK8Q8usb-phy@47401300ti,am335x-usb-phyG@phyvokay8K9Q9usb@47401000ti,musb-am33xxvokayG@G@ mccontrolmchost , <I9h}:::::::::: : : : : ::::::::::: : : : : :rx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15usb-phy@47401b00ti,am335x-usb-phyG@phyvokay8K;Q;usb@47401800ti,musb-am33xxvokayG@G@ mccontrolmcotg , <I;h}::::::::::::::::::::::::::::::rx1rx2rx3rx4rx5rx6rx7rx8rx9rx10rx11rx12rx13rx14rx15tx1tx2tx3tx4tx5tx6tx7tx8tx9tx10tx11tx12tx13tx14tx15dma-controller@47402000ti,am3359-cppi41 G@G@ G@0G@@@#gluecontrollerschedulerqueuemgrglue;N\vokayK:Q:epwmss@48300000ti,am33xx-pwmssH0epwmss0 vdisabled$'H0H0H0H0H0H0ecap@48300100ti,am33xx-ecapjH0ecap0ecap0 vdisabledehrpwm@48300200ti,am33xx-ehrpwmjH0ehrpwm0 vdisabledepwmss@48302000ti,am33xx-pwmssH0 epwmss1 vdisabled$'H0!H0!H0!H0!H0"H0"ecap@48302100ti,am33xx-ecapjH0!/ecap1ecap1 vdisabledehrpwm@48302200ti,am33xx-ehrpwmjH0"ehrpwm1 vdisabledepwmss@48304000ti,am33xx-pwmssH0@epwmss2 vdisabled$'H0AH0AH0AH0AH0BH0Becap@48304100ti,am33xx-ecapjH0A=ecap2ecap2 vdisabledehrpwm@48304200ti,am33xx-ehrpwmjH0Behrpwm2 vdisabledethernet@4a100000ti,cpswcpgmac0<= fckcptsu @ πJJ&()*+'5vokaydefaultsleep>?mdio@4a101000ti,davinci_mdio davinci_mdio B@Jvokaydefaultsleep@AKBQBslave@4a100200 B'rmii0slave@4a100300 B 'rgmii-txid0cpsw-phy-sel@44e10650ti,am3352-cpsw-phy-selDP gmii-selCocmcram@40300000 mmio-sram@0wkup_m3@44d00000ti,am3353-wkup-m3D@D wkup_m3belm@48080000ti,am3352-elmH elmvokayKDQDlcdc@4830e000ti,am33xx-tilcdcH0&$lcdc vdisabledtscadc@44e0d000ti,am3359-tscadcD&adc_tsc vdisabledtscti,am3359-tscadcRti,am3359-adcgpmc@50000000ti,am3352-gpmcgpmcdP dwvokaydefaultC'nand@0,0 bch8polledtrue,,,;"N,ao(~6@RRtruetrue"9Q(c{Dsham@53100000ti,omap4-shamshamSm}%$rxvokayaes@53500000 ti,omap4-aesaesSPg}%%txrxvokaymcasp@48038000ti,am33xx-mcasp-audiomcasp0H F@mpudatPQtxrx vdisabled}%% txrxmcasp@4803C000ti,am33xx-mcasp-audiomcasp1H F@@mpudatRStxrx vdisabled}% % txrxrng@48310000 ti,omap4-rngrngH1 ofixedregulator@0regulator-fixed{vbatLK@LK@K/Q/fixedregulator@2defaultEregulator-fixed{vwl12712Z2Z ,pK2Q2 #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3serial4serial5d_can0d_can1usb0usb1phy0phy1ethernet0ethernet1device_typeregoperating-pointsvoltage-toleranceclocksclock-namesclock-latencycpu0-supplyinterruptsti,hwmodsranges#clock-cellsclock-frequencylinux,phandleti,max-divti,index-starts-at-oneclock-multclock-divti,set-rate-parentti,bit-shiftti,index-power-of-twopinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsinterrupt-controller#interrupt-cells#dma-cellsgpio-controller#gpio-cellsti,no-reset-on-initstatusdmasdma-namespinctrl-namespinctrl-0dtr-gpiosdsr-gpiosdcd-gpiosrng-gpioscts-gpiosrts-gpiosvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyti,en-ck32k-xtalregulator-compatibleregulator-always-onregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onpagesizeti,dual-voltti,needs-special-resetti,needs-special-hs-handlingvmmc-supplyti,non-removablebus-widthcap-power-off-card#hwlock-cellssyscon-raminit#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmti,spi-num-csreg-namesti,ctrl_modinterrupt-namesdr_modementor,multipointmentor,num-epsmentor,ram-bitsmentor,powerphys#dma-channels#dma-requests#pwm-cellscpdma_channelsale_entriesbd_ram_sizeno_bd_ramrx_descsmac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftsysconpinctrl-1dual_emacbus_freqmac-addressphy_idphy-modedual_emac_res_vlanrmii-clock-ext#io-channel-cellsti,no-idle-on-initgpmc,num-csgpmc,num-waitpinsnand-bus-widthti,nand-ecc-optti,nand-xfer-typegpmc,device-nandgpmc,device-widthgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wait-on-readgpmc,wait-on-writegpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,clk-activation-nsgpmc,wait-monitoring-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nselm_idgpiostartup-delay-usenable-active-high