;88h(H80)STMicroelectronics STM32F769-DISCO board !st,stm32f769-discost,stm32f769interrupt-controller@e000e100!arm,armv7m-nvic,AR Vtimer@e000e010!arm,armv7m-systickR^okay esoc !simple-busl}timer@40000000!st,stm32-timerR@ e ^disabledtimers@40000000!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@1!st,stm32-timer-triggerR ^disabledtimer@40000400!st,stm32-timerR@ e ^disabledtimers@40000400!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@2!st,stm32-timer-triggerR ^disabledtimer@40000800!st,stm32-timerR@ e ^disabledtimers@40000800!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@3!st,stm32-timer-triggerR ^disabledtimer@40000c00!st,stm32-timerR@ 2 etimers@40000c00!st,stm32-timersR@  eint ^disabledpwm !st,stm32-pwm ^disabledtimer@4!st,stm32-timer-triggerR ^disabledtimer@40001000!st,stm32-timerR@6 e ^disabledtimers@40001000!st,stm32-timersR@ eint ^disabledtimer@5!st,stm32-timer-triggerR ^disabledtimer@40001400!st,stm32-timerR@7 e ^disabledtimers@40001400!st,stm32-timersR@ eint ^disabledtimer@6!st,stm32-timer-triggerR ^disabledtimers@40001800!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@11!st,stm32-timer-triggerR  ^disabledtimers@40001c00!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimers@40002000!st,stm32-timersR@  eint ^disabledpwm !st,stm32-pwm ^disabledrtc@40002800 !st,stm32-rtcR@( e  lalarm ^okayserial@40004400!st,stm32f7-uartR@D& e ^disabledserial@40004800!st,stm32f7-uartR@H' e ^disabledserial@40004c00!st,stm32f7-uartR@L4 e ^disabledserial@40005000!st,stm32f7-uartR@P5 e ^disabledi2c@40005400!st,stm32f7-i2cR@T  e^okaydefaulti2c@40005800!st,stm32f7-i2cR@X!" e ^disabledi2c@40005C00!st,stm32f7-i2cR@\HI e ^disabledi2c@40006000!st,stm32f7-i2cR@`_` e ^disabledcec@40006c00 !st,stm32-cecR@l^e cechdmi-cec^okaydefaultserial@40007800!st,stm32f7-uartR@xR e ^disabledserial@40007c00!st,stm32f7-uartR@|S e ^disabledtimers@40010000!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@0!st,stm32-timer-triggerR ^disabledtimers@40010400!st,stm32-timersR@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@7!st,stm32-timer-triggerR ^disabledserial@40011000!st,stm32f7-uartR@% e^okaydefaultserial@40011400!st,stm32f7-uartR@G e ^disabledsdio2@40011c00!arm,pl180arm,primecell5R@ e apb_pclkgLl^okayZ f odefaultopendrain y sdio1@40012c00!arm,pl180arm,primecell5R@, e apb_pclk1Ll ^disabledsystem-config@40013800!sysconR@8Vinterrupt-controller@40013c00!st,stm32-exti,AR@<8 ()*>LVtimers@40014000!st,stm32-timersR@@ eint ^disabledpwm !st,stm32-pwm ^disabledtimer@8!st,stm32-timer-triggerR ^disabledtimers@40014400!st,stm32-timersR@D eint ^disabledpwm !st,stm32-pwm ^disabledtimers@40014800!st,stm32-timersR@H eint ^disabledpwm !st,stm32-pwm ^disabledpower-config@40007000!sysconR@pVcrc@40023000!st,stm32f7-crcR@0 e  ^disabledrcc@40023800/!st,stm32f769-rccst,stm32f746-rccst,stm32-rccR@8e  B@Vdma-controller@40026000 !st,stm32-dmaR@` / e ^disableddma-controller@40026400 !st,stm32-dmaR@d 89:;<DEF e ^disabledusb@40040000!st,stm32f7-hsotgR@M eotg  @@@@ ^okayotg  usb2-phydefaultusb@50000000!st,stm32f4x9-fsotgRPC e'otg ^disabledpin-controller }@0l!st,stm32f769-pinctrlgpio@40020000+;,AR eGGPIOAVgpio@40020400+;,AR eGGPIOBgpio@40020800+;,AR eGGPIOCgpio@40020c00+;,AR  eGGPIODgpio@40021000+;,AR eGGPIOEgpio@40021400+;,AR eGGPIOFgpio@40021800+;,AR eGGPIOGgpio@40021c00+;,AR eGGPIOHgpio@40022000+;,AR  eGGPIOIV gpio@40022400+;,AR$ e GGPIOJVgpio@40022800+;,AR( e GGPIOKcec-0VpinsT[evusart1-0Vpins1T v[pins2T vusart1-1pins1T v[pins2Tvi2c1-0VpinsTve[usbotg-hs-0Vpins0Tt          v[usbotg-hs-1pins0Tt "          v[usbotg-fs-0pins T v[sdio-pins-a-0pinsT( ) * + , 2 [sdio-pins-od-a-0pins1T( ) * + , [pins2T2 e[sdio-pins-b-0V pinsTi j   6 7 [sdio-pins-od-b-0V pins1Ti j   6 [pins2T7 e[clocksclk-hse !fixed-clock}x@V clk-lse !fixed-clockclk-lsi !fixed-clock}clk-i2s-ckin !fixed-clocklV chosenroot=/dev/ramserial0:115200n8memory@c0000000memoryRaliases/soc/serial@40011000leds !gpio-ledsgreen i heartbeatred i gpio_keys !gpio-keysbutton@0Userf iusb-phy!usb-nop-xceiv e main_clkVmmc_vcard!regulator-fixed  mmc_vcard2Z02ZV #address-cells#size-cellsmodelcompatibleinterrupt-controller#interrupt-cellsregphandlestatusclocksinterrupt-parentrangesinterruptsclock-names#pwm-cellsassigned-clocksassigned-clock-parentsinterrupt-namesst,syscfgresetspinctrl-0pinctrl-namesi2c-scl-rising-time-nsi2c-scl-falling-time-nsarm,primecell-periphidmax-frequencyvmmc-supplycd-gpiosbroken-cdpinctrl-1bus-width#reset-cells#clock-cellsassigned-clock-rates#dma-cellsst,mem2memg-rx-fifo-sizeg-np-tx-fifo-sizeg-tx-fifo-sizedr_modephysphy-namespins-are-numberedgpio-controller#gpio-cellsst,bank-namepinmuxslew-ratedrive-open-drainbias-disabledrive-push-pullclock-frequencybootargsstdout-pathdevice_typeserial0linux,default-triggerautorepeatlabellinux,code#phy-cellsregulator-nameregulator-min-microvoltregulator-max-microvolt