8( google,veyron-minnie-rev4google,veyron-minnie-rev3google,veyron-minnie-rev2google,veyron-minnie-rev1google,veyron-minnie-rev0google,veyron-minniegoogle,veyronrockchip,rk3288&7Google Minniealiases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhcpu-opp-tableoperating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\bus simple-busdma-controller@ff250000arm,pl330arm,primecell%@; apb_pclkhdma-controller@ff600000arm,pl330arm,primecell`@; apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@; apb_pclkhkreserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6$timer@ff810000rockchip,rk3288-timer  H ; a timerpclkdisplay-subsystemrockchip,display-subsystem; mmc@ff0c0000rockchip,rk3288-dw-mshcAр ;Drvbiuciuciu-driveciu-sampleO  @Zresetokayfp  Z %default3mmc@ff0d0000rockchip,rk3288-dw-mshcAр ;Eswbiuciuciu-driveciu-sampleO ! @Zresetokayf=J`k%default 3 mmc@ff0e0000rockchip,rk3288-dw-mshcAр ;Ftxbiuciuciu-driveciu-sampleO "@Zreset disabledmmc@ff0f0000rockchip,rk3288-dw-mshcAр ;Guybiuciuciu-driveciu-sampleO #@Zresetokayfpy`k%default 3saradc@ff100000rockchip,saradc $;I[saradcapb_pclkW Zsaradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk  txrx ,%default3 !"#okayec@0google,cros-ec-spi& %default3$-i2c-tunnelgoogle,cros-ec-i2c-tunnelbq27500@55 ti,bq27500Ukeyboard-controllergoogle,cros-ec-keyb  @'};0DY1 d>"A#( C  \=@V B |)<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk txrx -%default3%&'( disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclktxrx .%default3)*+,okay4 flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;M%default3-okayG2_dtpm@20infineon,slb9645tt vi2c@ff150000rockchip,rk3288-i2c ?i2c;O%default3.okayG2_,touchscreen@10elan,ekth3500&/%default301 /22i2c@ff160000rockchip,rk3288-i2c @i2c;P%default33okayG2_,ts3a227e@3b ti,ts3a227e;&4%default35htrackpad@15elan,ekth3000& %default367i2c@ff170000rockchip,rk3288-i2c Ai2c;Q%default38 disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclktxrx%default 39:;okaybluetooth%default 3<=>brcm,bcm43540-bt ? ? ?$-.serial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclktxrx%default3@okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclk%default3Aokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclktxrx%default3B disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclk  txrx%default3C disabledthermal-zonesreserve_thermalE[iDcpu_thermalEd[iDtripscpu_alert0yppassivehEcpu_alert1y$passivehFcpu_crity criticalcooling-mapsmap0E0map1F0gpu_thermalEd[iDtripsgpu_alert0y4passivehGgpu_crity criticalcooling-mapsmap0G Htsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk Ztsadc-apb%initdefaultsleep3IJIKHokay hDethernet@ff290000rockchip,rk3288-gmac)$macirqeth_wake_irqK8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB Zstmmaceth disabledusb@ff500000 generic-ehciP ;4L9usbokayCusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otgYhost4M 9usb2-phyaokayxusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otgYhost@@ 4N 9usb2-phyokayzNxusb@ff5c0000 generic-ehci\ ; disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;L%default3OokayG2_dpmic@1brockchip,rk808xin32kwifibt_32kin&4%default 3PQR+7SCO[h7uSShregulatorsDCDC_REG1vdd_arm q qh regulator-state-memDCDC_REG2vdd_gpu 5qhregulator-state-memDCDC_REG3 vcc135_ddrregulator-state-mem.DCDC_REG4vcc_18w@w@hregulator-state-mem.Fw@LDO_REG1 vcc33_io2Z2Zh7regulator-state-mem.F2ZLDO_REG3vdd_10B@B@regulator-state-mem.FB@LDO_REG7vdd10_lcd_pwren_h&%&%regulator-state-memSWITCH_REG1 vcc33_lcdhiregulator-state-memLDO_REG6 vcc18_codecw@w@hjregulator-state-memLDO_REG4 vccio_sdw@2Zhregulator-state-memLDO_REG5 vcc33_sd2Z2Zhregulator-state-memLDO_REG8 vcc33_ccd2Z2Zregulator-state-memLDO_REG22Z2Z vcc33_touchh2regulator-state-memSWITCH_REG2 vcc5v_touchregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c;N%default3TokayG2_ max98090@10maxim,max98090&Umclk;q%default3Vhpwm@ff680000rockchip,rk3288-pwmhb%default3W;_pwmokayhpwm@ff680010rockchip,rk3288-pwmhb%default3X;_pwmokayhpwm@ff680020rockchip,rk3288-pwmh b%default3Y;_pwm disabledpwm@ff680030rockchip,rk3288-pwmh0b%default3Z;_pwm disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controllermh hnpd_vio@9 ;chgfdehilkj$[\]^_`abcpd_hevc@11 ;opdepd_video@12 ;fpd_gpu@13 ;ghreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvKHjk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhKedp-phyrockchip,rk3288-dp-phy;h24mokayh~io-domains"rockchip,rk3288-io-voltage-domainokay7  7 %7 3i ? Kj Xusbphyrockchip,rk3288-usb-phyokayusb-phy@320 ;]phyclk Zphy-resethNusb-phy@3344;^phyclk Zphy-resethLusb-phy@348H;_phyclk Zphy-resethMwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif f;T mclkhclkktx 6%default3lK disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s f 5;Ri2s_clki2s_hclkkktxrx%default3m w okayhcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk Zcrypto-rstokayiommu@ff900800rockchip,iommu@ $iep_mmu; aclkiface  disablediommu@ff914000rockchip,iommu @P $isp_mmu; aclkiface   disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk n ilm Zcoreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop n def Zaxiahbdclk ookayporth endpoint@0 phendpoint@1 qhendpoint@2 rhyendpoint@3 sh|iommu@ff930300rockchip,iommu  $vopb_mmu; aclkiface n  okayhovop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop n  Zaxiahbdclk tokayporth endpoint@0 uhendpoint@1 vhendpoint@2 whzendpoint@3 xh}iommu@ff940300rockchip,iommu  $vopl_mmu; aclkiface n  okayhtmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk n K disabledportsportendpoint@0 yhrendpoint@1 zhwlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvds%lcdc3{ n K disabledportsport@0endpoint@0 |hsendpoint@1 }hxdp@ff970000rockchip,rk3288-dp@ b;icdppclk4~9dpoZdpKokay%default3portsport@0endpoint@0 hqendpoint@1 hvport@1endpoint@0 hhdmi@ff980000rockchip,rk3288-dw-hdmi fK g;hmniahbisfrcec n okay%defaultunwedge3hportsportendpoint@0 hpendpoint@1 huvideo-codec@ff9a0000rockchip,rk3288-vpu   $vepuvdpu; aclkhclk  n iommu@ff9a0800rockchip,iommu $vpu_mmu; aclkiface  n hiommu@ff9c0440rockchip,iommu @@@ o $hevc_mmu; aclkiface  disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ $jobmmugpu;  n okay hHgpu-opp-tableoperating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000syscon hgqos@ffaa0080syscon hhqos@ffad0000syscon h\qos@ffad0100syscon h]qos@ffad0180syscon h^qos@ffad0400syscon h_qos@ffad0480syscon h`qos@ffad0500syscon h[qos@ffad0800syscon haqos@ffad0880syscon hbqos@ffad0900syscon hcqos@ffae0000syscon hfqos@ffaf0000syscon hdqos@ffaf0080syscon heefuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   hpinctrlrockchip,rk3288-pinctrlK%defaultsleep3gpio0@ff750000rockchip,gpio-banku Q;@ + ;   GPMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh4gpio1@ff780000rockchip,gpio-bankx R;A + ;  gpio2@ff790000rockchip,gpio-banky S;B + ;   GCONFIG0CONFIG1CONFIG2CONFIG3PROCHOT#EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENTOUCH_INTTOUCH_RSTI2C3_SCL_TPI2C3_SDA_TPh/gpio3@ff7a0000rockchip,gpio-bankz T;C + ;   GFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio4@ff7b0000rockchip,gpio-bank{ U;D + ;   GUART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKdev_wakeWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEh?gpio5@ff7c0000rockchip,gpio-bank| V;E + ;  U GVolum_Up#Volum_Down#SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio6@ff7d0000rockchip,gpio-bank} W;F + ;   GI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhUgpio7@ff7e0000rockchip,gpio-bank~ X;G + ;   GLCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVS_OKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio8@ff7f0000rockchip,gpio-bank Y;H + ;  ^ GRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 Whdmi-cec-c7 Whdmi-ddc Whhdmi-ddc-unwedge Whvcc50-hdmi-en Whpcfg-output-low ehpcfg-pull-up phpcfg-pull-down }hpcfg-pull-none hpcfg-pull-none-12ma  hsleepglobal-pwroff Whddrio-pwroff Whddr0-retention Whddr1-retention Wedpedp-hpd W hi2c0i2c0-xfer WhOi2c1i2c1-xfer Wh-i2c2i2c2-xfer W  hTi2c3i2c3-xfer Wh.i2c4i2c4-xfer Wh3i2c5i2c5-xfer Wh8i2s0i2s0-bus` Whmlcdclcdc-ctl@ Wh{sdmmcsdmmc-clk Whsdmmc-cmd Whsdmmc-cd Wsdmmc-bus1 Wsdmmc-bus4@ Whsdmmc-cd-disabled Whsdmmc-cd-gpio Whsdio0sdio0-bus1 Wsdio0-bus4@ Whsdio0-cmd Whsdio0-clk Whsdio0-cd Wsdio0-wp Wsdio0-pwr Wsdio0-bkpwr Wsdio0-int Wwifienable-h Whbt-enable-l Wh=bt-host-wake Wbt-host-wake-l Wh<bt-dev-wake-sleep Wbt-dev-wake-awake Wbt-dev-wake Wh>sdio1sdio1-bus1 Wsdio1-bus4@ Wsdio1-cd Wsdio1-wp Wsdio1-bkpwr Wsdio1-int Wsdio1-cmd Wsdio1-clk Wsdio1-pwr W emmcemmc-clk Whemmc-cmd Whemmc-pwr W emmc-bus1 Wemmc-bus4@ Wemmc-bus8 Whemmc-reset W hspi0spi0-clk W h spi0-cs0 W h#spi0-tx Wh!spi0-rx Wh"spi0-cs1 Wspi1spi1-clk W h%spi1-cs0 W h(spi1-rx Wh'spi1-tx Wh&spi2spi2-cs1 Wspi2-clk Wh)spi2-cs0 Wh,spi2-rx Wh+spi2-tx W h*uart0uart0-xfer Wh9uart0-cts Wh:uart0-rts Wh;uart1uart1-xfer W h@uart1-cts W uart1-rts W uart2uart2-xfer WhAuart3uart3-xfer WhBuart3-cts W uart3-rts W uart4uart4-xfer WhCuart4-cts W uart4-rts W tsadcotp-gpio W hIotp-out W hJpwm0pwm0-pin WhWpwm1pwm1-pin WhXpwm2pwm2-pin WhYpwm3pwm3-pin WhZgmacrgmii-pins W rmii-pins Wspdifspdif-tx W hlpcfg-pull-none-drv-8ma  hpcfg-pull-up-drv-8ma p pcfg-output-high hbuttonspwr-key-l Whap-lid-int-l Whvolum-down-l W hvolum-up-l W hpmicpmic-int-l WhPdvs-1 W hQdvs-2 WhRrebootap-warm-reset-h W hrecovery-switchrec-mode-l W tpmtpm-int-h Wwrite-protectfw-wp-ap Wcodechp-det Whint-codec WhVmic-det W hheadsetts3a227e-int-l Wh5backlightbl_pwr_en W hbl-en Whlcdlcd-en Whavdd-1v8-disp-en W hchargerac-present-ap Whcros-ecec-int Wh$suspendsuspend-l-wake Whsuspend-l-sleep Whtrackpadtrackpad-int Wh6usb-hosthost1-pwr-en W husbotg-pwren-h W hbuck-5vdrv-5v Whprochotgpio-prochot Wtouchscreentouch-int Wh0touch-rst Wh1chosen serial2:115200n8memorymemorypower-button gpio-keys%default3power Power 4 t dgpio-restart gpio-restart 4 %default3 emmc-pwrseqmmc-pwrseq-emmc3%default / hsdio-pwrseqmmc-pwrseq-simple; ext_clock%default3 ?hvcc-5vregulator-fixedvcc_5vLK@LK@   %default3hSvcc33-sysregulator-fixed vcc33_sys2Z2Z hvcc50-hdmiregulator-fixed vcc50_hdmi S  %default3vdd-logicpwm-regulator vdd_logic   { 3~psound!rockchip,rockchip-audio-max98090%default3 FVEYRON-I2S U m U U   backlight-regulatorregulator-fixed  / %default3backlight_regulator  :hpanel-regulatorregulator-fixed  %default3panel_regulator hvcc18-lcdregulator-fixed  / %default3 vcc18_lcd backlightpwm-backlight    - %default3 B@ :  O  `hpanelauo,b101ean01okay ` mpanel-timing@ w        portsportendpoint hgpio-charger gpio-charger mains 4%default3lid-switch gpio-keys%default3lid Lid 4   vccsysregulator-fixedvccsyshvcc5-host1-regulatorregulator-fixed  4 %default3 vcc5_host1vcc5v-otg-regulatorregulator-fixed  4 %default3 vcc5_host2volume-buttons gpio-keys%default3volum_down Volum_down   r dvolum_up Volum_up   s d #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-buskeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreset-gpiosvcc33-supplyvccio-supplyti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-paramspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenvactivevfront-porchvback-porchvsync-lencharger-typelinux,input-type