\8V(V`$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/serial@11010000E/serial@11020000M/serial@11030000U/spi@11090000cpuscpu@f00Zcpu,arm,cortex-a7fjq@pscicpu@f01Zcpu,arm,cortex-a7fjqpscicpu@f02Zcpu,arm,cortex-a7fjqpscicpu@f03Zcpu,arm,cortex-a7fjqpsciopp_table0,operating-points-v2opp-408000000Q~@opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxopp-1296000000M?d7opp-1392000000R<opp-1464000000WB\bus ,simple-buspdma@110f0000,arm,pl330arm,primecellf@ $apb_pclk arm-pmu,arm,cortex-a7-pmu0LMNO0psci,arm,psci-1.0arm,psci-0.2smctimer,arm,armv7-timerC0   gn6oscillator ,fixed-clockgn6wxin24m"display-subsystem,rockchip,display-subsystem i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ $i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf @ $i2s_clki2s_hclkP txrx disabledspdif@100d0000,rockchip,rk3228-spdiff  S $mclkhclk txdefault  disabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2sf@ $i2s_clki2s_hclkR txrx disabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfdf#io-domains",rockchip,rk3228-io-voltage-domainokay  usb2-phy@760,rockchip,rk3228-usb2phyf` $phyclk wusb480m_phy0okay:otg-port$;<=otg-bvalidotg-idlinestateokay9host-port > linestateokay;usb2-phy@800,rockchip,rk3228-usb2phyf $phyclk wusb480m_phy1okay<otg-port D linestateokay=host-port E linestateokay>serial@11010000,snps,dw-apb-uartf 7gn6MU$baudclkapb_pclkdefault % disabledserial@11020000,snps,dw-apb-uartf 8gn6NV$baudclkapb_pclkdefault% disabledserial@11030000,snps,dw-apb-uartf 9gn6OW$baudclkapb_pclkdefault%okayefuse@11040000,rockchip,rk3228-efusef G $pclk_efuseid@7fcpu_leakage@17fi2c@11050000,rockchip,rk3228-i2cf $$i2cLdefault disabledi2c@11060000,rockchip,rk3228-i2cf %$i2cMdefault disabledi2c@11070000,rockchip,rk3228-i2cf &$i2cNdefault disabledi2c@11080000,rockchip,rk3228-i2cf '$i2cOdefault disabledspi@11090000,rockchip,rk3228-spif  1AR$spiclkapb_pclkdefault disabledwatchdog@110a0000 ,snps,dw-wdtf  (b disabledpwm@110b0000,rockchip,rk3288-pwmf 2^$pwmdefault disabledpwm@110b0010,rockchip,rk3288-pwmf 2^$pwmdefaultokayKpwm@110b0020,rockchip,rk3288-pwmf 2^$pwmdefault okayLpwm@110b0030,rockchip,rk3288-pwmf 02^$pwmdefault! disabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timerf  + "a $timerpclkclock-controller@110e0000,rockchip,rk3228-cruf=#JHWkb$g#g0,eррxhррxhthermal-zonescpu-thermal|d$tripscpu_alert0papassive%cpu_alert1$apassive&cpu_crit_ acriticalcooling-mapsmap0%0map1&0tsadc@11150000,rockchip,rk3228-tsadcf :HX$tsadcapb_pclkWHgjW tsadc-apbinitdefaultsleep'('sokay($hdmi-phy@12030000,rockchip,rk3228-hdmi-phyfm"$sysclkrefoclkrefpclk whdmiphy_phy disabled+gpu@20000000",rockchip,rk3228-maliarm,mali-400f Hgpgpmmupp0ppmmu0pp1ppmmu1 $buscorej~ disablediommu@20020800,rockchip,iommuf   vpu_mmu $aclkiface? disablediommu@20030480,rockchip,iommuf @ @  vdec_mmu $aclkiface? disabledvop@20050000,rockchip,rk3228-vopf   $aclk_vopdclk_vophclk_vopjdef axiahbdclkK) disabledport endpoint@0fR*/iommu@20053f00,rockchip,iommuf ?  vop_mmu $aclkifaceb disabled)rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rgaf  !$aclkhclksclkjkmn coreaxiahbiommu@20070800,rockchip,iommuf  iep_mmu $aclkiface? disabledhdmi@200a0000,rockchip,rk3228-dw-hdmif % #Wo+{l$isfriahbcecdefault ,-.j`hdmi+hdmi=# disabledportsportendpoint@0fR/*mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Drv$biuciuciu-driveciu-sampledefault 012 disabledmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@   Esw$biuciuciu-driveciu-sampledefault 345 disabledmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshcf0@ g<4`<4` Guy$biuciuciu-driveciu-sampledefault 678jSresetokayusb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc2f0 $otgotg@ 9 usb2-phyokayusb@30080000 ,generic-ehcif0  :;usbokayusb@300a0000 ,generic-ohcif0   :;usbokayusb@300c0000 ,generic-ehcif0   <=usbokayusb@300e0000 ,generic-ohcif0  <=usbokayusb@30100000 ,generic-ehcif0 B <>usbokayusb@30120000 ,generic-ohcif0 C <>usbokayethernet@30200000,rockchip,rk3228-gmacf0  macirq8~oM$stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macj8 stmmaceth=#okayW}~ o?}.input@;rgmiidefaultA DBT j'B@0interrupt-controller@32010000 ,arm,gic-400 f22 2@ 2`   pinctrl,rockchip,rk3228-pinctrl=#gpio0@11110000,rockchip,gpio-bankf 3@gpio1@11120000,rockchip,gpio-bankf 4Agpio2@11130000,rockchip,gpio-bankf 5BBgpio3@11140000,rockchip,gpio-bankf 6CGpcfg-pull-upFpcfg-pull-downEpcfg-pull-noneDpcfg-pull-none-drv-12ma Csdmmcsdmmc-clk C0sdmmc-cmd C1sdmmc-bus4@ CCCC2sdiosdio-clk C3sdio-cmd C4sdio-bus4@ CCCC5emmcemmc-clk D6emmc-cmd D7emmc-bus8 DDDDDDDD8gmacrgmii-pins D DDCCCC C CDDDD DDArmii-pins D DDCC CDDDDphy-pins  DDhdmihdmi-hpd E-hdmii2c-xfer  DD,hdmi-cec D.i2c0i2c0-xfer  DDi2c1i2c1-xfer  DDi2c2i2c2-xfer  DDi2c3i2c3-xfer  DDspi0spi0-clk Fspi0-cs0 Fspi0-tx Fspi0-rx Fspi0-cs1  Fspi1spi1-clk Fspi1-cs0 Fspi1-rx Fspi1-tx Fspi1-cs1 Fi2s1i2s1-bus D D D D DDDDD pwm0pwm0-pin Dpwm1pwm1-pin Dpwm2pwm2-pin  D pwm3pwm3-pin  D!spdifspdif-tx D tsadcotp-gpio D'otp-out D(uart0uart0-xfer  DDuart0-cts Duart0-rts Duart1uart1-xfer   D Duart1-cts Duart1-rts  Duart2uart2-xfer  FDuart21-xfer   F Duart2-cts Duart2-rts Dkeyspwr-key FMusbhost-vbus-drv DHmemory@60000000Zmemoryf`@dc-12v-regulator,regulator-fixeddc_12v(<NfJext_gmac ,fixed-clockgsY@ wext_gmac?vcc-host-regulator,regulator-fixed~ OGdefaultH vcc_host(<Ivcc-phy-regulator,regulator-fixed~vcc_phyNw@fw@(<@vcc-sys-regulator,regulator-fixedvcc_sys(<NLK@fLK@JIvccio-1v8-regulator,regulator-fixed vccio_1v8Nw@fw@(Ivccio-3v3-regulator,regulator-fixed vccio_3v3N2Zf2Z(I vdd-arm-regulator,pwm-regulatorKaIvdd_armN~f\(<vdd-log-regulator,pwm-regulatorLaIvdd_logNB@f (<gpio_keys ,gpio-keysdefaultMpower-keyGPIO Key Power Gtd #address-cells#size-cellsinterrupt-parentcompatiblemodelserial0serial1serial2spi0device_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supplyinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modeiommu-cellsiommusremote-endpoint#iommu-cellsassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeednon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source