8( Dgumstix,omap3-overo-alto35gumstix,omap3-overoti,omap3430ti,omap3 +!7OMAP35xx Gumstix Overo on Alto35chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000%d/ocp@68000000/spi@48098000/display@1cpus+cpu@0arm,cortex-a8mcpuy}cpupmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+!>defaultLVpinmux_uart2_pins ^<>@BVpinmux_i2c1_pins^Vpinmux_mmc1_pins0^Vpinmux_mmc2_pins0^(*,.02Vpinmux_w3cbw003c_pins^lVpinmux_hsusb2_pins@^      Vpinmux_twl4030_pins^AVpinmux_i2c3_pins^Vpinmux_uart3_pins^npVpinmux_dss_dpi_pins^V pinmux_lb035_pins^DVpinmux_backlight_pins^FVpinmux_mcspi1_pins(^Vpinmux_ads7846_pins^ Vpinmux_led_pins ^LPRVscm_conf@270sysconsimple-busyp0+ p0Vpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyrpbias_mmc_omap2430ypbias_mmc_omap2430w@-Vclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhV mcbsp5_fckti,composite-clock} Vmcbsp1_mux_fck@4ti,composite-mux-clock}yV mcbsp1_fckti,composite-clock} Vmcbsp2_mux_fck@4ti,composite-mux-clock} yVmcbsp2_fckti,composite-clock} Vmcbsp3_mux_fck@68ti,composite-mux-clock} yhVmcbsp3_fckti,composite-clock}Vmcbsp4_mux_fck@68ti,composite-mux-clock} yhVmcbsp4_fckti,composite-clock}Vclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+!pinmux_twl4030_vpins ^Vpinmux_button_pins^Vaes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYVosc_sys_ck@d40 ti,mux-clock}y @Vsys_ck@1270ti,divider-clock}ypVsys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}Vdpll4_x2_ckfixed-factor-clock}corex2_fckfixed-factor-clock}V wkup_l4_ickfixed-factor-clock}VOcorex2_d3_fckfixed-factor-clock} Vcorex2_d5_fckfixed-factor-clock} Vclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockVAvirt_12m_ck fixed-clockVvirt_13m_ck fixed-clock]@Vvirt_19200000_ck fixed-clock$Vvirt_26000000_ck fixed-clockVvirt_38_4m_ck fixed-clockIVdpll4_ck@d00ti,omap3-dpll-per-clock}y D 0Vdpll4_m2_ck@d48ti,divider-clock}?y HV!dpll4_m2x2_mul_ckfixed-factor-clock}!V"dpll4_m2x2_ck@d00ti,gate-clock}"y (V#omap_96m_alwon_fckfixed-factor-clock}#V*dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0Vdpll3_m3_ck@1140ti,divider-clock}y@V$dpll3_m3x2_mul_ckfixed-factor-clock}$V%dpll3_m3x2_ck@d00ti,gate-clock}% y (V&emu_core_alwon_ckfixed-factor-clock}&Vcsys_altclk fixed-clockV/mcbsp_clks fixed-clockVdpll3_m2_ck@d40ti,divider-clock}y @Vcore_ckfixed-factor-clock}V'dpll1_fck@940ti,divider-clock}'y @V(dpll1_ck@904ti,omap3-dpll-clock}(y  $ @ 4Vdpll1_x2_ckfixed-factor-clock}V)dpll1_x2m2_ck@944ti,divider-clock})y DV=cm_96m_fckfixed-factor-clock}*V+omap_96m_fck@d40 ti,mux-clock}+y @VFdpll4_m3_ck@e40ti,divider-clock} y@V,dpll4_m3x2_mul_ckfixed-factor-clock},V-dpll4_m3x2_ck@d00ti,gate-clock}-y (V.omap_54m_fck@d40 ti,mux-clock}./y @V9cm_96m_d2_fckfixed-factor-clock}+V0omap_48m_fck@d40 ti,mux-clock}0/y @V1omap_12m_fckfixed-factor-clock}1VHdpll4_m4_ck@e40ti,divider-clock}y@V2dpll4_m4x2_mul_ckti,fixed-factor-clock}2>LYV3dpll4_m4x2_ck@d00ti,gate-clock}3y (YVdpll4_m5_ck@f40ti,divider-clock}?y@V4dpll4_m5x2_mul_ckti,fixed-factor-clock}4>LYV5dpll4_m5x2_ck@d00ti,gate-clock}5y (YVkdpll4_m6_ck@1140ti,divider-clock}?y@V6dpll4_m6x2_mul_ckfixed-factor-clock}6V7dpll4_m6x2_ck@d00ti,gate-clock}7y (V8emu_per_alwon_ckfixed-factor-clock}8Vdclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}'y pV:clkout2_src_mux_ck@d70ti,composite-mux-clock}'+9y pV;clkout2_src_ckti,composite-clock}:;V<sys_clkout2@d70ti,divider-clock}<@y plmpu_ckfixed-factor-clock}=V>arm_fck@924ti,divider-clock}>y $emu_mpu_alwon_ckfixed-factor-clock}>Vel3_ick@a40ti,divider-clock}'y @V?l4_ick@a40ti,divider-clock}?y @V@rm_ick@c40ti,divider-clock}@y @gpt10_gate_fck@a00ti,composite-gate-clock} y VBgpt10_mux_fck@a40ti,composite-mux-clock}Ay @VCgpt10_fckti,composite-clock}BCgpt11_gate_fck@a00ti,composite-gate-clock} y VDgpt11_mux_fck@a40ti,composite-mux-clock}Ay @VEgpt11_fckti,composite-clock}DEcore_96m_fckfixed-factor-clock}FVmmchs2_fck@a00ti,wait-gate-clock}y Vmmchs1_fck@a00ti,wait-gate-clock}y Vi2c3_fck@a00ti,wait-gate-clock}y Vi2c2_fck@a00ti,wait-gate-clock}y Vi2c1_fck@a00ti,wait-gate-clock}y Vmcbsp5_gate_fck@a00ti,composite-gate-clock} y Vmcbsp1_gate_fck@a00ti,composite-gate-clock} y V core_48m_fckfixed-factor-clock}1VGmcspi4_fck@a00ti,wait-gate-clock}Gy Vmcspi3_fck@a00ti,wait-gate-clock}Gy Vmcspi2_fck@a00ti,wait-gate-clock}Gy Vmcspi1_fck@a00ti,wait-gate-clock}Gy Vuart2_fck@a00ti,wait-gate-clock}Gy Vuart1_fck@a00ti,wait-gate-clock}Gy  Vcore_12m_fckfixed-factor-clock}HVIhdq_fck@a00ti,wait-gate-clock}Iy Vcore_l3_ickfixed-factor-clock}?VJsdrc_ick@a10ti,wait-gate-clock}Jy Vgpmc_fckfixed-factor-clock}Jcore_l4_ickfixed-factor-clock}@VKmmchs2_ick@a10ti,omap3-interface-clock}Ky Vmmchs1_ick@a10ti,omap3-interface-clock}Ky Vhdq_ick@a10ti,omap3-interface-clock}Ky Vmcspi4_ick@a10ti,omap3-interface-clock}Ky Vmcspi3_ick@a10ti,omap3-interface-clock}Ky Vmcspi2_ick@a10ti,omap3-interface-clock}Ky Vmcspi1_ick@a10ti,omap3-interface-clock}Ky Vi2c3_ick@a10ti,omap3-interface-clock}Ky Vi2c2_ick@a10ti,omap3-interface-clock}Ky Vi2c1_ick@a10ti,omap3-interface-clock}Ky Vuart2_ick@a10ti,omap3-interface-clock}Ky Vuart1_ick@a10ti,omap3-interface-clock}Ky  Vgpt11_ick@a10ti,omap3-interface-clock}Ky  Vgpt10_ick@a10ti,omap3-interface-clock}Ky  Vmcbsp5_ick@a10ti,omap3-interface-clock}Ky  Vmcbsp1_ick@a10ti,omap3-interface-clock}Ky  Vomapctrl_ick@a10ti,omap3-interface-clock}Ky Vdss_tv_fck@e00ti,gate-clock}9yVdss_96m_fck@e00ti,gate-clock}FyVdss2_alwon_fck@e00ti,gate-clock}yVdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y VLgpt1_mux_fck@c40ti,composite-mux-clock}Ay @VMgpt1_fckti,composite-clock}LMVaes2_ick@a10ti,omap3-interface-clock}Ky Vwkup_32k_fckfixed-factor-clock}AVNgpio1_dbck@c00ti,gate-clock}Ny Vsha12_ick@a10ti,omap3-interface-clock}Ky Vwdt2_fck@c00ti,wait-gate-clock}Ny Vwdt2_ick@c10ti,omap3-interface-clock}Oy Vwdt1_ick@c10ti,omap3-interface-clock}Oy Vgpio1_ick@c10ti,omap3-interface-clock}Oy Vomap_32ksync_ick@c10ti,omap3-interface-clock}Oy Vgpt12_ick@c10ti,omap3-interface-clock}Oy Vgpt1_ick@c10ti,omap3-interface-clock}Oy Vper_96m_fckfixed-factor-clock}*V per_48m_fckfixed-factor-clock}1VPuart3_fck@1000ti,wait-gate-clock}Py Vgpt2_gate_fck@1000ti,composite-gate-clock}yVQgpt2_mux_fck@1040ti,composite-mux-clock}Ay@VRgpt2_fckti,composite-clock}QRVgpt3_gate_fck@1000ti,composite-gate-clock}yVSgpt3_mux_fck@1040ti,composite-mux-clock}Ay@VTgpt3_fckti,composite-clock}STgpt4_gate_fck@1000ti,composite-gate-clock}yVUgpt4_mux_fck@1040ti,composite-mux-clock}Ay@VVgpt4_fckti,composite-clock}UVgpt5_gate_fck@1000ti,composite-gate-clock}yVWgpt5_mux_fck@1040ti,composite-mux-clock}Ay@VXgpt5_fckti,composite-clock}WXgpt6_gate_fck@1000ti,composite-gate-clock}yVYgpt6_mux_fck@1040ti,composite-mux-clock}Ay@VZgpt6_fckti,composite-clock}YZgpt7_gate_fck@1000ti,composite-gate-clock}yV[gpt7_mux_fck@1040ti,composite-mux-clock}Ay@V\gpt7_fckti,composite-clock}[\gpt8_gate_fck@1000ti,composite-gate-clock} yV]gpt8_mux_fck@1040ti,composite-mux-clock}Ay@V^gpt8_fckti,composite-clock}]^gpt9_gate_fck@1000ti,composite-gate-clock} yV_gpt9_mux_fck@1040ti,composite-mux-clock}Ay@V`gpt9_fckti,composite-clock}_`per_32k_alwon_fckfixed-factor-clock}AVagpio6_dbck@1000ti,gate-clock}ayVgpio5_dbck@1000ti,gate-clock}ayVgpio4_dbck@1000ti,gate-clock}ayVgpio3_dbck@1000ti,gate-clock}ayVgpio2_dbck@1000ti,gate-clock}ay Vwdt3_fck@1000ti,wait-gate-clock}ay Vper_l4_ickfixed-factor-clock}@Vbgpio6_ick@1010ti,omap3-interface-clock}byVgpio5_ick@1010ti,omap3-interface-clock}byVgpio4_ick@1010ti,omap3-interface-clock}byVgpio3_ick@1010ti,omap3-interface-clock}byVgpio2_ick@1010ti,omap3-interface-clock}by Vwdt3_ick@1010ti,omap3-interface-clock}by Vuart3_ick@1010ti,omap3-interface-clock}by Vuart4_ick@1010ti,omap3-interface-clock}byVgpt9_ick@1010ti,omap3-interface-clock}by Vgpt8_ick@1010ti,omap3-interface-clock}by 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Vsha11_ick@a14ti,omap3-interface-clock}jy des1_ick@a14ti,omap3-interface-clock}jy cam_mclk@f00ti,gate-clock}kyYcam_ick@f10!ti,omap3-no-wait-interface-clock}@yVcsi2_96m_fck@f00ti,gate-clock}yVsecurity_l3_ickfixed-factor-clock}?Vlpka_ick@a14ti,omap3-interface-clock}ly icr_ick@a10ti,omap3-interface-clock}Ky des2_ick@a10ti,omap3-interface-clock}Ky mspro_ick@a10ti,omap3-interface-clock}Ky mailboxes_ick@a10ti,omap3-interface-clock}Ky ssi_l4_ickfixed-factor-clock}@Vssr1_fck@c00ti,wait-gate-clock}y Vsr2_fck@c00ti,wait-gate-clock}y Vsr_l4_ickfixed-factor-clock}@dpll2_fck@40ti,divider-clock}'y@Vmdpll2_ck@4ti,omap3-dpll-clock}my$@4Vndpll2_m2_ck@44ti,divider-clock}nyDVoiva2_ck@0ti,wait-gate-clock}oyVmodem_fck@a00ti,omap3-interface-clock}y Vsad2d_ick@a10ti,omap3-interface-clock}?y Vmad2d_ick@a18ti,omap3-interface-clock}?y Vmspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock} y Vpssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock} y @$Vqssi_ssr_fck_3430es2ti,composite-clock}pqVrssi_sst_fck_3430es2fixed-factor-clock}rV hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Jy Vssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}sy V usim_gate_fck@c00ti,composite-gate-clock}F y V~sys_d2_ckfixed-factor-clock}Vuomap_96m_d2_fckfixed-factor-clock}FVvomap_96m_d4_fckfixed-factor-clock}FVwomap_96m_d8_fckfixed-factor-clock}FVxomap_96m_d10_fckfixed-factor-clock}F Vydpll5_m2_d4_ckfixed-factor-clock}tVzdpll5_m2_d8_ckfixed-factor-clock}tV{dpll5_m2_d16_ckfixed-factor-clock}tV|dpll5_m2_d20_ckfixed-factor-clock}tV}usim_mux_fck@c40ti,composite-mux-clock(}uvwxyz{|}y @Vusim_fckti,composite-clock}~usim_ick@c10ti,omap3-interface-clock}Oy  Vdpll5_ck@d04ti,omap3-dpll-clock}y  $ L 4Vdpll5_m2_ck@d50ti,divider-clock}y PVtsgx_gate_fck@b00ti,composite-gate-clock}'y Vcore_d3_ckfixed-factor-clock}'Vcore_d4_ckfixed-factor-clock}'Vcore_d6_ckfixed-factor-clock}'Vomap_192m_alwon_fckfixed-factor-clock}#Vcore_d2_ckfixed-factor-clock}'Vsgx_mux_fck@b40ti,composite-mux-clock }+y @Vsgx_fckti,composite-clock}Vsgx_ick@b10ti,wait-gate-clock}?y Vcpefuse_fck@a08ti,gate-clock}y Vts_fck@a08ti,gate-clock}Ay Vusbtll_fck@a08ti,wait-gate-clock}ty Vusbtll_ick@a18ti,omap3-interface-clock}Ky Vmmchs3_ick@a10ti,omap3-interface-clock}Ky Vmmchs3_fck@a00ti,wait-gate-clock}y Vdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yYVdss_ick_3430es2@e10ti,omap3-dss-interface-clock}@yVusbhost_120m_fck@1400ti,gate-clock}tyVusbhost_48m_fck@1400ti,dss-gate-clock}1yVusbhost_ick@1410ti,omap3-dss-interface-clock}@yVclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}gdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}nd2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }target-module@48320000ti,sysc-omap2ti,syscyH2H2 revsysc}Nfckick+ H2counter@0ti,omap-counter32ky interrupt-controller@48200000ti,omap3-intcyH Vtarget-module@48056000ti,sysc-omap2ti,syscyH`H`,H`(revsyscsyss#  }Jick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdmay  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,disabledsham@480c3000ti,omap3-shamshamyH 0d1Erxtarget-module@48318000ti,sysc-omap2-timerti,syscyH1H1H1revsyscsyss' }fckick+ H1;Otimer@0ti,omap3430-timery}fck%ZiyAtarget-module@49032000ti,sysc-omap2-timerti,syscyI I I revsyscsyss' }fckick+ I timer@0ti,omap3430-timery&timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11target-module@48304000ti,sysc-omap2-timerti,syscyH0@H0@H0@revsyscsyss' }fckick+ H0@timer@0ti,omap3430-timery_Zusbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ ehci-phy ,disabledohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHMgpmc@6e000000ti,omap3430-gpmcgpmcynrxtx+3C00+,Vnand@0,0ti,omap2-nandmicron,mt29c4g96maz y 0bch8@Q_,q,",(6@RR ( +partition@0SPLypartition@80000U-Bootypartition@1c0000 Environmenty$partition@280000Kernely(partition@780000 Filesystemyusb_otg_hs@480ab000ti,omap3-musbyH \] mcdma usb_otg_hs 1 < D  M \   dusb2-phy n2dss@48050000 ti,omap3-dssyH,ok dss_core}fck+>defaultL dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll ,disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH ,disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  ,disabled dss_venc}fckportendpoint  tVssi-controller@48058000 ti,omap3-ssissi,okyHHsysgddG gdd_mpu+ }r   ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrxCDssi-port@4805b000ti,omap3-ssi-portyHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+!>defaultLpinmux_hsusb2_2_pins0^   " Vpinmux_w3cbw003c_2_pins^Visp@480bc000 ti,omap3-ispyH H | rl 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b'Vlis33-3v3-regregulator-fixedylis33-3v3-reg2Z2ZVlis33-1v8-regregulator-fixedylis33-1v8-regw@w@Vads7846-regregulator-fixed yads7846-reg2Z2ZVbacklightgpio-backlight>defaultL  leds gpio-leds>defaultLgpio148overo:red:gpio148 gpio150overo:yellow:gpio150 gpio151overo:blue:gpio151 gpio170overo:green:gpio170  gpio_keys gpio-keys+>defaultLbutton0button0    compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-cslabelspi-max-frequencyspi-cpolspi-cphaenable-gpiosremote-endpointvcc-supplypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourceti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspstartup-delay-usenable-active-highreset-gpiosdefault-onlinux,code