t84( @Uheadacoustics,omap3-ha-lcdtechnexion,omap3-tao3530ti,omap3430ti,omap34xxti,omap3 +77TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpupmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+-Jdefault X pinmux_hsusbb2_pins`b          vpinmux_mmc1_pinsPb "$&vpinmux_mmc2_pins0b(*,.02vpinmux_wlan_gpiob^pinmux_uart3_pinsbnApvpinmux_i2c3_pinsbvpinmux_mcspi1_pins bvpinmux_mcspi3_pins bvpinmux_mcbsp3_pins b<>@Bvpinmux_twl4030_pinsbAvpinmux_sound2_pinsbnpinmux_led_blue_pinsbv pinmux_led_green_pinsbv pinmux_led_red_pinsbv pinmux_poweroff_pinsbvpinmux_powerdown_input_pinsbvfpga_boot0_pins bvfpga_boot1_pins brtvxvpinmux_touchscreen_irq_pinsb4pinmux_touchscreen_wake_pinsbv pinmux_dss_dpi_pinsbv pinmux_lte430_pinsb8vpinmux_backlight_pinsb:vscm_conf@270sysconsimple-busyp0+ p0v pbias_regulator@2b0ti,pbias-omap3ti,pbias-omapy~ pbias_mmc_omap2430pbias_mmc_omap2430w@-vclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhvmcbsp5_fckti,composite-clock}vmcbsp1_mux_fck@4ti,composite-mux-clock}yvmcbsp1_fckti,composite-clock}vmcbsp2_mux_fck@4ti,composite-mux-clock}yvmcbsp2_fckti,composite-clock}vmcbsp3_mux_fck@68ti,composite-mux-clock}yhvmcbsp3_fckti,composite-clock}vmcbsp4_mux_fck@68ti,composite-mux-clock}yhvmcbsp4_fckti,composite-clock}vclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+-pinmux_twl4030_vpins bvaes@480c5000 ti,omap3-aesaesyH PPABtxrx disabledprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYv!osc_sys_ck@d40 ti,mux-clock} !y @v"sys_ck@1270ti,divider-clock}"ypv'sys_clkout1@d70ti,gate-clock}"y pdpll3_x2_ckfixed-factor-clock}#&1dpll3_m2x2_ckfixed-factor-clock}$&1v&dpll4_x2_ckfixed-factor-clock}%&1corex2_fckfixed-factor-clock}&&1v(wkup_l4_ickfixed-factor-clock}'&1vWcorex2_d3_fckfixed-factor-clock}(&1vcorex2_d5_fckfixed-factor-clock}(&1vclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockvIvirt_12m_ck fixed-clockvvirt_13m_ck fixed-clock]@vvirt_19200000_ck fixed-clock$vvirt_26000000_ck fixed-clockvvirt_38_4m_ck fixed-clockIv dpll4_ck@d00ti,omap3-dpll-per-clock}''y D 0v%dpll4_m2_ck@d48ti,divider-clock}%?y Hv)dpll4_m2x2_mul_ckfixed-factor-clock})&1v*dpll4_m2x2_ck@d00ti,gate-clock}*y ;v+omap_96m_alwon_fckfixed-factor-clock}+&1v2dpll3_ck@d00ti,omap3-dpll-core-clock}''y @ 0v#dpll3_m3_ck@1140ti,divider-clock}#y@v,dpll3_m3x2_mul_ckfixed-factor-clock},&1v-dpll3_m3x2_ck@d00ti,gate-clock}- y ;v.emu_core_alwon_ckfixed-factor-clock}.&1vksys_altclk fixed-clockv7mcbsp_clks fixed-clockvdpll3_m2_ck@d40ti,divider-clock}#y @v$core_ckfixed-factor-clock}$&1v/dpll1_fck@940ti,divider-clock}/y @v0dpll1_ck@904ti,omap3-dpll-clock}'0y  $ @ 4vdpll1_x2_ckfixed-factor-clock}&1v1dpll1_x2m2_ck@944ti,divider-clock}1y DvEcm_96m_fckfixed-factor-clock}2&1v3omap_96m_fck@d40 ti,mux-clock}3'y @vNdpll4_m3_ck@e40ti,divider-clock}% y@v4dpll4_m3x2_mul_ckfixed-factor-clock}4&1v5dpll4_m3x2_ck@d00ti,gate-clock}5y ;v6omap_54m_fck@d40 ti,mux-clock}67y @vAcm_96m_d2_fckfixed-factor-clock}3&1v8omap_48m_fck@d40 ti,mux-clock}87y @v9omap_12m_fckfixed-factor-clock}9&1vPdpll4_m4_ck@e40ti,divider-clock}%y@v:dpll4_m4x2_mul_ckti,fixed-factor-clock}:Q_lv;dpll4_m4x2_ck@d00ti,gate-clock};y ;lvdpll4_m5_ck@f40ti,divider-clock}%?y@v<dpll4_m5x2_mul_ckti,fixed-factor-clock}<Q_lv=dpll4_m5x2_ck@d00ti,gate-clock}=y ;lvsdpll4_m6_ck@1140ti,divider-clock}%?y@v>dpll4_m6x2_mul_ckfixed-factor-clock}>&1v?dpll4_m6x2_ck@d00ti,gate-clock}?y ;v@emu_per_alwon_ckfixed-factor-clock}@&1vlclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}/y pvBclkout2_src_mux_ck@d70ti,composite-mux-clock}/'3Ay pvCclkout2_src_ckti,composite-clock}BCvDsys_clkout2@d70ti,divider-clock}D@y pmpu_ckfixed-factor-clock}E&1vFarm_fck@924ti,divider-clock}Fy $emu_mpu_alwon_ckfixed-factor-clock}F&1vml3_ick@a40ti,divider-clock}/y @vGl4_ick@a40ti,divider-clock}Gy @vHrm_ick@c40ti,divider-clock}Hy @gpt10_gate_fck@a00ti,composite-gate-clock}' y vJgpt10_mux_fck@a40ti,composite-mux-clock}I'y @vKgpt10_fckti,composite-clock}JKgpt11_gate_fck@a00ti,composite-gate-clock}' y vLgpt11_mux_fck@a40ti,composite-mux-clock}I'y @vMgpt11_fckti,composite-clock}LMcore_96m_fckfixed-factor-clock}N&1vmmchs2_fck@a00ti,wait-gate-clock}y vmmchs1_fck@a00ti,wait-gate-clock}y vi2c3_fck@a00ti,wait-gate-clock}y vi2c2_fck@a00ti,wait-gate-clock}y vi2c1_fck@a00ti,wait-gate-clock}y vmcbsp5_gate_fck@a00ti,composite-gate-clock} y vmcbsp1_gate_fck@a00ti,composite-gate-clock} y vcore_48m_fckfixed-factor-clock}9&1vOmcspi4_fck@a00ti,wait-gate-clock}Oy vmcspi3_fck@a00ti,wait-gate-clock}Oy vmcspi2_fck@a00ti,wait-gate-clock}Oy vmcspi1_fck@a00ti,wait-gate-clock}Oy vuart2_fck@a00ti,wait-gate-clock}Oy vuart1_fck@a00ti,wait-gate-clock}Oy  vcore_12m_fckfixed-factor-clock}P&1vQhdq_fck@a00ti,wait-gate-clock}Qy vcore_l3_ickfixed-factor-clock}G&1vRsdrc_ick@a10ti,wait-gate-clock}Ry vgpmc_fckfixed-factor-clock}R&1core_l4_ickfixed-factor-clock}H&1vSmmchs2_ick@a10ti,omap3-interface-clock}Sy vmmchs1_ick@a10ti,omap3-interface-clock}Sy vhdq_ick@a10ti,omap3-interface-clock}Sy vmcspi4_ick@a10ti,omap3-interface-clock}Sy vmcspi3_ick@a10ti,omap3-interface-clock}Sy vmcspi2_ick@a10ti,omap3-interface-clock}Sy vmcspi1_ick@a10ti,omap3-interface-clock}Sy vi2c3_ick@a10ti,omap3-interface-clock}Sy vi2c2_ick@a10ti,omap3-interface-clock}Sy vi2c1_ick@a10ti,omap3-interface-clock}Sy vuart2_ick@a10ti,omap3-interface-clock}Sy vuart1_ick@a10ti,omap3-interface-clock}Sy  vgpt11_ick@a10ti,omap3-interface-clock}Sy  vgpt10_ick@a10ti,omap3-interface-clock}Sy  vmcbsp5_ick@a10ti,omap3-interface-clock}Sy  vmcbsp1_ick@a10ti,omap3-interface-clock}Sy  vomapctrl_ick@a10ti,omap3-interface-clock}Sy vdss_tv_fck@e00ti,gate-clock}Ayvdss_96m_fck@e00ti,gate-clock}Nyvdss2_alwon_fck@e00ti,gate-clock}'yvdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}'y vTgpt1_mux_fck@c40ti,composite-mux-clock}I'y @vUgpt1_fckti,composite-clock}TUvaes2_ick@a10ti,omap3-interface-clock}Sy vwkup_32k_fckfixed-factor-clock}I&1vVgpio1_dbck@c00ti,gate-clock}Vy vsha12_ick@a10ti,omap3-interface-clock}Sy vwdt2_fck@c00ti,wait-gate-clock}Vy vwdt2_ick@c10ti,omap3-interface-clock}Wy vwdt1_ick@c10ti,omap3-interface-clock}Wy vgpio1_ick@c10ti,omap3-interface-clock}Wy vomap_32ksync_ick@c10ti,omap3-interface-clock}Wy vgpt12_ick@c10ti,omap3-interface-clock}Wy vgpt1_ick@c10ti,omap3-interface-clock}Wy vper_96m_fckfixed-factor-clock}2&1vper_48m_fckfixed-factor-clock}9&1vXuart3_fck@1000ti,wait-gate-clock}Xy vgpt2_gate_fck@1000ti,composite-gate-clock}'yvYgpt2_mux_fck@1040ti,composite-mux-clock}I'y@vZgpt2_fckti,composite-clock}YZvgpt3_gate_fck@1000ti,composite-gate-clock}'yv[gpt3_mux_fck@1040ti,composite-mux-clock}I'y@v\gpt3_fckti,composite-clock}[\gpt4_gate_fck@1000ti,composite-gate-clock}'yv]gpt4_mux_fck@1040ti,composite-mux-clock}I'y@v^gpt4_fckti,composite-clock}]^gpt5_gate_fck@1000ti,composite-gate-clock}'yv_gpt5_mux_fck@1040ti,composite-mux-clock}I'y@v`gpt5_fckti,composite-clock}_`gpt6_gate_fck@1000ti,composite-gate-clock}'yvagpt6_mux_fck@1040ti,composite-mux-clock}I'y@vbgpt6_fckti,composite-clock}abgpt7_gate_fck@1000ti,composite-gate-clock}'yvcgpt7_mux_fck@1040ti,composite-mux-clock}I'y@vdgpt7_fckti,composite-clock}cdgpt8_gate_fck@1000ti,composite-gate-clock}' yvegpt8_mux_fck@1040ti,composite-mux-clock}I'y@vfgpt8_fckti,composite-clock}efgpt9_gate_fck@1000ti,composite-gate-clock}' yvggpt9_mux_fck@1040ti,composite-mux-clock}I'y@vhgpt9_fckti,composite-clock}ghper_32k_alwon_fckfixed-factor-clock}I&1vigpio6_dbck@1000ti,gate-clock}iyvgpio5_dbck@1000ti,gate-clock}iyvgpio4_dbck@1000ti,gate-clock}iyvgpio3_dbck@1000ti,gate-clock}iyvgpio2_dbck@1000ti,gate-clock}iy vwdt3_fck@1000ti,wait-gate-clock}iy vper_l4_ickfixed-factor-clock}H&1vjgpio6_ick@1010ti,omap3-interface-clock}jyvgpio5_ick@1010ti,omap3-interface-clock}jyvgpio4_ick@1010ti,omap3-interface-clock}jyvgpio3_ick@1010ti,omap3-interface-clock}jyvgpio2_ick@1010ti,omap3-interface-clock}jy vwdt3_ick@1010ti,omap3-interface-clock}jy vuart3_ick@1010ti,omap3-interface-clock}jy vuart4_ick@1010ti,omap3-interface-clock}jyvgpt9_ick@1010ti,omap3-interface-clock}jy vgpt8_ick@1010ti,omap3-interface-clock}jy vgpt7_ick@1010ti,omap3-interface-clock}jyvgpt6_ick@1010ti,omap3-interface-clock}jyvgpt5_ick@1010ti,omap3-interface-clock}jyvgpt4_ick@1010ti,omap3-interface-clock}jyvgpt3_ick@1010ti,omap3-interface-clock}jyvgpt2_ick@1010ti,omap3-interface-clock}jyvmcbsp2_ick@1010ti,omap3-interface-clock}jyvmcbsp3_ick@1010ti,omap3-interface-clock}jyvmcbsp4_ick@1010ti,omap3-interface-clock}jyvmcbsp2_gate_fck@1000ti,composite-gate-clock}yvmcbsp3_gate_fck@1000ti,composite-gate-clock}yvmcbsp4_gate_fck@1000ti,composite-gate-clock}yvemu_src_mux_ck@1140 ti,mux-clock}'klmy@vnemu_src_ckti,clkdm-gate-clock}nvopclk_fck@1140ti,divider-clock}oy@pclkx2_fck@1140ti,divider-clock}oy@atclk_fck@1140ti,divider-clock}oy@traceclk_src_fck@1140 ti,mux-clock}'klmy@vptraceclk_fck@1140ti,divider-clock}p y@secure_32k_fck fixed-clockvqgpt12_fckfixed-factor-clock}q&1vwdt1_fckfixed-factor-clock}q&1security_l4_ick2fixed-factor-clock}H&1vraes1_ick@a14ti,omap3-interface-clock}ry rng_ick@a14ti,omap3-interface-clock}ry vsha11_ick@a14ti,omap3-interface-clock}ry des1_ick@a14ti,omap3-interface-clock}ry cam_mclk@f00ti,gate-clock}sylcam_ick@f10!ti,omap3-no-wait-interface-clock}Hyvcsi2_96m_fck@f00ti,gate-clock}yvsecurity_l3_ickfixed-factor-clock}G&1vtpka_ick@a14ti,omap3-interface-clock}ty icr_ick@a10ti,omap3-interface-clock}Sy des2_ick@a10ti,omap3-interface-clock}Sy mspro_ick@a10ti,omap3-interface-clock}Sy mailboxes_ick@a10ti,omap3-interface-clock}Sy ssi_l4_ickfixed-factor-clock}H&1v{sr1_fck@c00ti,wait-gate-clock}'y vsr2_fck@c00ti,wait-gate-clock}'y vsr_l4_ickfixed-factor-clock}H&1dpll2_fck@40ti,divider-clock}/y@vudpll2_ck@4ti,omap3-dpll-clock}'uy$@4vvdpll2_m2_ck@44ti,divider-clock}vyDvwiva2_ck@0ti,wait-gate-clock}wyvmodem_fck@a00ti,omap3-interface-clock}'y vsad2d_ick@a10ti,omap3-interface-clock}Gy vmad2d_ick@a18ti,omap3-interface-clock}Gy vmspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}(y vxssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}(y @$vyssi_ssr_fck_3430es2ti,composite-clock}xyvzssi_sst_fck_3430es2fixed-factor-clock}z&1v hsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Ry vssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}{y v usim_gate_fck@c00ti,composite-gate-clock}N y vsys_d2_ckfixed-factor-clock}'&1v}omap_96m_d2_fckfixed-factor-clock}N&1v~omap_96m_d4_fckfixed-factor-clock}N&1vomap_96m_d8_fckfixed-factor-clock}N&1vomap_96m_d10_fckfixed-factor-clock}N&1 vdpll5_m2_d4_ckfixed-factor-clock}|&1vdpll5_m2_d8_ckfixed-factor-clock}|&1vdpll5_m2_d16_ckfixed-factor-clock}|&1vdpll5_m2_d20_ckfixed-factor-clock}|&1vusim_mux_fck@c40ti,composite-mux-clock(}'}~y @vusim_fckti,composite-clock}usim_ick@c10ti,omap3-interface-clock}Wy  vdpll5_ck@d04ti,omap3-dpll-clock}''y  $ L 4vdpll5_m2_ck@d50ti,divider-clock}y Pv|sgx_gate_fck@b00ti,composite-gate-clock}/y vcore_d3_ckfixed-factor-clock}/&1vcore_d4_ckfixed-factor-clock}/&1vcore_d6_ckfixed-factor-clock}/&1vomap_192m_alwon_fckfixed-factor-clock}+&1vcore_d2_ckfixed-factor-clock}/&1vsgx_mux_fck@b40ti,composite-mux-clock }3y @vsgx_fckti,composite-clock}vsgx_ick@b10ti,wait-gate-clock}Gy vcpefuse_fck@a08ti,gate-clock}'y vts_fck@a08ti,gate-clock}Iy vusbtll_fck@a08ti,wait-gate-clock}|y vusbtll_ick@a18ti,omap3-interface-clock}Sy vmmchs3_ick@a10ti,omap3-interface-clock}Sy vmmchs3_fck@a00ti,wait-gate-clock}y vdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}ylvdss_ick_3430es2@e10ti,omap3-dss-interface-clock}Hyvusbhost_120m_fck@1400ti,gate-clock}|yvusbhost_48m_fck@1400ti,dss-gate-clock}9yvusbhost_ick@1410ti,omap3-dss-interface-clock}Hyvclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}#dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}odpll4_clkdmti,clockdomain}%wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}vd2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }target-module@48320000ti,sysc-omap2ti,syscyH2H2 revsysc}Vfckick+ H2counter@0ti,omap-counter32ky interrupt-controller@48200000ti,omap3-intcyH vtarget-module@48056000ti,sysc-omap2ti,syscyH`H`,H`(revsyscsyss#  }Rick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdmay  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vregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0vregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5vregulator-vusb1v8ti,twl4030-vusb1v8vregulator-vusb3v1ti,twl4030-vusb3v1vregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-vgpioti,twl4030-gpioFVvtwl4030-usbti,twl4030-usb  v pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad"2madcti,twl4030-madcEvi2c@48072000 ti,omap3-i2cyH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cyH=txrx+i2c3JdefaultXmailbox@48094000ti,omap3-mailboxmailboxyH @Wcudsp  spi@48098000ti,omap2-mcspiyH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3JdefaultXspidev@0spidevlyspi@4809a000ti,omap2-mcspiyH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3 tx0rx0tx1rx1JdefaultXspidev@0spidevlyspi@480ba000ti,omap2-mcspiyH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrxJdefaultX mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrxJdefaultX mmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400-ti,omap2-iommuyH mmu_isp:vmmu@5d000000-ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< JcommontxrxZmcbsp1 txrx}fck disabledtarget-module@480a0000ti,sysc-omap2ti,syscyH <H @H Drevsyscsyss}ick+ H rng@0 ti,omap2-rngy 4mcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?JcommontxrxsidetoneZmcbsp2mcbsp2_sidetone!"txrx}fckickokayvmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZJcommontxrxsidetoneZmcbsp3mcbsp3_sidetonetxrx}fckickokayJdefaultXmcbsp@49026000ti,omap3-mcbspyI`mpu 67 JcommontxrxZmcbsp4txrx}fcki disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR JcommontxrxZmcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erx disabledtarget-module@48318000ti,sysc-omap2-timerti,syscyH1H1H1revsyscsyss' }fckick+ H1ztimer@0ti,omap3430-timery}fck%Itarget-module@49032000ti,sysc-omap2-timerti,syscyI I I revsyscsyss' }fckick+ I timer@0ti,omap3430-timery&timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11target-module@48304000ti,sysc-omap2-timerti,syscyH0@H0@H0@revsyscsyss' }fckick+ H0@timer@0ti,omap3430-timery_usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3yHDLehci@48064800 ti,ehci-omapyHHMgpmc@6e000000ti,omap3430-gpmcgpmcynrxtx!-+FV0vnand@0,0ti,omap2-nand y ?N`swp~$$$0H"H36B+x-loader@0 TX-Loaderybootloaders@80000TU-Bootybootloaders_env@260000 TU-Boot Envy&kernel@280000TKernely(@filesystem@680000 TFile Systemyhusb_otg_hs@480ab000ti,omap3-musbyH \]Jmcdma usb_otg_hsZem v   usb2-phy2dss@48050000 ti,omap3-dssyHok dss_core}fck+JdefaultX dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint vssi-controller@48058000 ti,omap3-ssissiokyHHsysgddGJgdd_mpu+ }z   ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrxCDssi-port@4805b000ti,omap3-ssi-portyHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$+-isp@480bc000 ti,omap3-ispyH H |~ lports+bandgap@48002524yH%$ti,omap34xx-bandgapvtarget-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreyH $sysc}fck+ H smartreflex@0ti,omap3-smartreflex-coreytarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivayH $sysc}fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivaytarget-module@50000000ti,sysc-omap2ti,syscyPrev}fckick+ P@opp-tableoperating-points-v2-ti-cpu~ vopp1-125000000sY@ opp2-250000000沀 g8g8g8opp3-500000000e OOOopp4-550000000 U txtxtxopp5-600000000#F pppopp6-720000000*T pppthermal-zonescpu_thermal4BN Omemory@80000000mmemoryyhsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z _dpvhsusb2_phyusb-nop-xceiv u vsoundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixedregulator-mmc2-sdio-poweron00 _d'vgpio_poweroffJdefaultXgpio-poweroff display panel-dpiTlcdJdefaultX  portendpointv panel-timingP (V     %backlightgpio-backlightJdefaultX   5 compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2cpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesstatusclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyspi-cphati,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on