28( X2logicpd,dm3730-som-lv-devkitti,omap3630ti,omap3 ++7LogicPD Zoom DM3730 SOM-LV Development Kitchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000 l/displaycpus+cpu@0arm,cortex-a8ucpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+ "@]defaultkupinmux_mm3_pins0}468:upinmux_mcbsp2_pins } upinmux_uart2_pins(}DFHJhupinmux_mcspi1_pins }upinmux_hsusb2_pins0}      upinmux_hsusb_otg_pins`}rtvxz|~upinmux_i2c1_pins}upinmux_i2c2_pins}upinmux_i2c3_pins}upinmux_tsc2004_pins}Vupinmux_twl4030_pins}Aupinmux_gpio_key_pins}upinmux_led_pins}.u!pinmux_lan9221_pins}Tu pinmux_mmc1_pins@}upinmux_lcd_enable_pin}Zu#pinmux_dss_dpi_pins1}uscm_conf@270sysconsimple-busp0+ p0upbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-uclocks+mcbsp5_mux_fck@68ti,composite-mux-clock hu mcbsp5_fckti,composite-clock umcbsp1_mux_fck@4ti,composite-mux-clock u mcbsp1_fckti,composite-clock umcbsp2_mux_fck@4ti,composite-mux-clock umcbsp2_fckti,composite-clockumcbsp3_mux_fck@68ti,composite-mux-clock humcbsp3_fckti,composite-clockumcbsp4_mux_fck@68ti,composite-mux-clock humcbsp4_fckti,composite-clockuclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ "@]defaultkpinmux_hsusb1_reset_pin}upinmux_wl127x_gpio_pin}  upinmux_twl4030_vpins }upinmux_led_pins_wkup}$u"pinmux_backlight_pins}u&aes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYuosc_sys_ck@d40 ti,mux-clock @usys_ck@1270ti,divider-clockpu"sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock2=dpll3_m2x2_ckfixed-factor-clock2=u!dpll4_x2_ckfixed-factor-clock 2=corex2_fckfixed-factor-clock!2=u#wkup_l4_ickfixed-factor-clock"2=uRcorex2_d3_fckfixed-factor-clock#2=ucorex2_d5_fckfixed-factor-clock#2=uclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockuDvirt_12m_ck fixed-clockuvirt_13m_ck fixed-clock]@uvirt_19200000_ck fixed-clock$uvirt_26000000_ck fixed-clockuvirt_38_4m_ck fixed-clockIudpll4_ck@d00ti,omap3-dpll-per-j-type-clock"" D 0u dpll4_m2_ck@d48ti,divider-clock ? Hu$dpll4_m2x2_mul_ckfixed-factor-clock$2=u%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock% Gu&omap_96m_alwon_fckfixed-factor-clock&2=u-dpll3_ck@d00ti,omap3-dpll-core-clock"" @ 0udpll3_m3_ck@1140ti,divider-clock@u'dpll3_m3x2_mul_ckfixed-factor-clock'2=u(dpll3_m3x2_ck@d00ti,hsdiv-gate-clock(  Gu)emu_core_alwon_ckfixed-factor-clock)2=ufsys_altclk fixed-clocku2mcbsp_clks fixed-clocku dpll3_m2_ck@d40ti,divider-clock @ucore_ckfixed-factor-clock2=u*dpll1_fck@940ti,divider-clock* @u+dpll1_ck@904ti,omap3-dpll-clock"+  $ @ 4udpll1_x2_ckfixed-factor-clock2=u,dpll1_x2m2_ck@944ti,divider-clock, Du@cm_96m_fckfixed-factor-clock-2=u.omap_96m_fck@d40 ti,mux-clock." @uIdpll4_m3_ck@e40ti,divider-clock  @u/dpll4_m3x2_mul_ckfixed-factor-clock/2=u0dpll4_m3x2_ck@d00ti,hsdiv-gate-clock0 Gu1omap_54m_fck@d40 ti,mux-clock12 @u<cm_96m_d2_fckfixed-factor-clock.2=u3omap_48m_fck@d40 ti,mux-clock32 @u4omap_12m_fckfixed-factor-clock42=uKdpll4_m4_ck@e40ti,divider-clock @u5dpll4_m4x2_mul_ckti,fixed-factor-clock5]kxu6dpll4_m4x2_ck@d00ti,gate-clock6 Gxudpll4_m5_ck@f40ti,divider-clock ?@u7dpll4_m5x2_mul_ckti,fixed-factor-clock7]kxu8dpll4_m5x2_ck@d00ti,hsdiv-gate-clock8 Gxundpll4_m6_ck@1140ti,divider-clock ?@u9dpll4_m6x2_mul_ckfixed-factor-clock92=u:dpll4_m6x2_ck@d00ti,hsdiv-gate-clock: Gu;emu_per_alwon_ckfixed-factor-clock;2=ugclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock* pu=clkout2_src_mux_ck@d70ti,composite-mux-clock*".< pu>clkout2_src_ckti,composite-clock=>u?sys_clkout2@d70ti,divider-clock?@ pmpu_ckfixed-factor-clock@2=uAarm_fck@924ti,divider-clockA $emu_mpu_alwon_ckfixed-factor-clockA2=uhl3_ick@a40ti,divider-clock* @uBl4_ick@a40ti,divider-clockB @uCrm_ick@c40ti,divider-clockC @gpt10_gate_fck@a00ti,composite-gate-clock"  uEgpt10_mux_fck@a40ti,composite-mux-clockD" @uFgpt10_fckti,composite-clockEFgpt11_gate_fck@a00ti,composite-gate-clock"  uGgpt11_mux_fck@a40ti,composite-mux-clockD" @uHgpt11_fckti,composite-clockGHcore_96m_fckfixed-factor-clockI2=ummchs2_fck@a00ti,wait-gate-clock ummchs1_fck@a00ti,wait-gate-clock ui2c3_fck@a00ti,wait-gate-clock ui2c2_fck@a00ti,wait-gate-clock ui2c1_fck@a00ti,wait-gate-clock umcbsp5_gate_fck@a00ti,composite-gate-clock   u mcbsp1_gate_fck@a00ti,composite-gate-clock   u core_48m_fckfixed-factor-clock42=uJmcspi4_fck@a00ti,wait-gate-clockJ umcspi3_fck@a00ti,wait-gate-clockJ umcspi2_fck@a00ti,wait-gate-clockJ umcspi1_fck@a00ti,wait-gate-clockJ uuart2_fck@a00ti,wait-gate-clockJ uuart1_fck@a00ti,wait-gate-clockJ  ucore_12m_fckfixed-factor-clockK2=uLhdq_fck@a00ti,wait-gate-clockL ucore_l3_ickfixed-factor-clockB2=uMsdrc_ick@a10ti,wait-gate-clockM ugpmc_fckfixed-factor-clockM2=core_l4_ickfixed-factor-clockC2=uNmmchs2_ick@a10ti,omap3-interface-clockN ummchs1_ick@a10ti,omap3-interface-clockN uhdq_ick@a10ti,omap3-interface-clockN umcspi4_ick@a10ti,omap3-interface-clockN umcspi3_ick@a10ti,omap3-interface-clockN umcspi2_ick@a10ti,omap3-interface-clockN umcspi1_ick@a10ti,omap3-interface-clockN ui2c3_ick@a10ti,omap3-interface-clockN ui2c2_ick@a10ti,omap3-interface-clockN ui2c1_ick@a10ti,omap3-interface-clockN uuart2_ick@a10ti,omap3-interface-clockN uuart1_ick@a10ti,omap3-interface-clockN  ugpt11_ick@a10ti,omap3-interface-clockN  ugpt10_ick@a10ti,omap3-interface-clockN  umcbsp5_ick@a10ti,omap3-interface-clockN  umcbsp1_ick@a10ti,omap3-interface-clockN  uomapctrl_ick@a10ti,omap3-interface-clockN udss_tv_fck@e00ti,gate-clock<udss_96m_fck@e00ti,gate-clockIudss2_alwon_fck@e00ti,gate-clock"udummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock" uOgpt1_mux_fck@c40ti,composite-mux-clockD" @uPgpt1_fckti,composite-clockOPuaes2_ick@a10ti,omap3-interface-clockN uwkup_32k_fckfixed-factor-clockD2=uQgpio1_dbck@c00ti,gate-clockQ usha12_ick@a10ti,omap3-interface-clockN uwdt2_fck@c00ti,wait-gate-clockQ uwdt2_ick@c10ti,omap3-interface-clockR uwdt1_ick@c10ti,omap3-interface-clockR ugpio1_ick@c10ti,omap3-interface-clockR uomap_32ksync_ick@c10ti,omap3-interface-clockR ugpt12_ick@c10ti,omap3-interface-clockR ugpt1_ick@c10ti,omap3-interface-clockR uper_96m_fckfixed-factor-clock-2=uper_48m_fckfixed-factor-clock42=uSuart3_fck@1000ti,wait-gate-clockS ugpt2_gate_fck@1000ti,composite-gate-clock"uTgpt2_mux_fck@1040ti,composite-mux-clockD"@uUgpt2_fckti,composite-clockTUu gpt3_gate_fck@1000ti,composite-gate-clock"uVgpt3_mux_fck@1040ti,composite-mux-clockD"@uWgpt3_fckti,composite-clockVWgpt4_gate_fck@1000ti,composite-gate-clock"uXgpt4_mux_fck@1040ti,composite-mux-clockD"@uYgpt4_fckti,composite-clockXYgpt5_gate_fck@1000ti,composite-gate-clock"uZgpt5_mux_fck@1040ti,composite-mux-clockD"@u[gpt5_fckti,composite-clockZ[gpt6_gate_fck@1000ti,composite-gate-clock"u\gpt6_mux_fck@1040ti,composite-mux-clockD"@u]gpt6_fckti,composite-clock\]gpt7_gate_fck@1000ti,composite-gate-clock"u^gpt7_mux_fck@1040ti,composite-mux-clockD"@u_gpt7_fckti,composite-clock^_gpt8_gate_fck@1000ti,composite-gate-clock" u`gpt8_mux_fck@1040ti,composite-mux-clockD"@uagpt8_fckti,composite-clock`agpt9_gate_fck@1000ti,composite-gate-clock" ubgpt9_mux_fck@1040ti,composite-mux-clockD"@ucgpt9_fckti,composite-clockbcper_32k_alwon_fckfixed-factor-clockD2=udgpio6_dbck@1000ti,gate-clockdugpio5_dbck@1000ti,gate-clockdugpio4_dbck@1000ti,gate-clockdugpio3_dbck@1000ti,gate-clockdugpio2_dbck@1000ti,gate-clockd uwdt3_fck@1000ti,wait-gate-clockd uper_l4_ickfixed-factor-clockC2=uegpio6_ick@1010ti,omap3-interface-clockeugpio5_ick@1010ti,omap3-interface-clockeugpio4_ick@1010ti,omap3-interface-clockeugpio3_ick@1010ti,omap3-interface-clockeugpio2_ick@1010ti,omap3-interface-clocke uwdt3_ick@1010ti,omap3-interface-clocke uuart3_ick@1010ti,omap3-interface-clocke uuart4_ick@1010ti,omap3-interface-clockeugpt9_ick@1010ti,omap3-interface-clocke ugpt8_ick@1010ti,omap3-interface-clocke ugpt7_ick@1010ti,omap3-interface-clockeugpt6_ick@1010ti,omap3-interface-clockeugpt5_ick@1010ti,omap3-interface-clockeugpt4_ick@1010ti,omap3-interface-clockeugpt3_ick@1010ti,omap3-interface-clockeugpt2_ick@1010ti,omap3-interface-clockeumcbsp2_ick@1010ti,omap3-interface-clockeumcbsp3_ick@1010ti,omap3-interface-clockeumcbsp4_ick@1010ti,omap3-interface-clockeumcbsp2_gate_fck@1000ti,composite-gate-clock umcbsp3_gate_fck@1000ti,composite-gate-clock umcbsp4_gate_fck@1000ti,composite-gate-clock uemu_src_mux_ck@1140 ti,mux-clock"fgh@uiemu_src_ckti,clkdm-gate-clockiujpclk_fck@1140ti,divider-clockj@pclkx2_fck@1140ti,divider-clockj@atclk_fck@1140ti,divider-clockj@traceclk_src_fck@1140 ti,mux-clock"fgh@uktraceclk_fck@1140ti,divider-clockk @secure_32k_fck fixed-clockulgpt12_fckfixed-factor-clockl2=u wdt1_fckfixed-factor-clockl2=security_l4_ick2fixed-factor-clockC2=umaes1_ick@a14ti,omap3-interface-clockm rng_ick@a14ti,omap3-interface-clockm usha11_ick@a14ti,omap3-interface-clockm des1_ick@a14ti,omap3-interface-clockm cam_mclk@f00ti,gate-clocknxcam_ick@f10!ti,omap3-no-wait-interface-clockCucsi2_96m_fck@f00ti,gate-clockusecurity_l3_ickfixed-factor-clockB2=uopka_ick@a14ti,omap3-interface-clocko icr_ick@a10ti,omap3-interface-clockN des2_ick@a10ti,omap3-interface-clockN mspro_ick@a10ti,omap3-interface-clockN mailboxes_ick@a10ti,omap3-interface-clockN ssi_l4_ickfixed-factor-clockC2=uvsr1_fck@c00ti,wait-gate-clock" usr2_fck@c00ti,wait-gate-clock" usr_l4_ickfixed-factor-clockC2=dpll2_fck@40ti,divider-clock*@updpll2_ck@4ti,omap3-dpll-clock"p$@4uqdpll2_m2_ck@44ti,divider-clockqDuriva2_ck@0ti,wait-gate-clockrumodem_fck@a00ti,omap3-interface-clock" usad2d_ick@a10ti,omap3-interface-clockB umad2d_ick@a18ti,omap3-interface-clockB umspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock# usssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock# @$utssi_ssr_fck_3430es2ti,composite-clockstuussi_sst_fck_3430es2fixed-factor-clocku2=uhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockM ussi_ick_3430es2@a10ti,omap3-ssi-interface-clockv uusim_gate_fck@c00ti,composite-gate-clockI  usys_d2_ckfixed-factor-clock"2=uxomap_96m_d2_fckfixed-factor-clockI2=uyomap_96m_d4_fckfixed-factor-clockI2=uzomap_96m_d8_fckfixed-factor-clockI2=u{omap_96m_d10_fckfixed-factor-clockI2= u|dpll5_m2_d4_ckfixed-factor-clockw2=u}dpll5_m2_d8_ckfixed-factor-clockw2=u~dpll5_m2_d16_ckfixed-factor-clockw2=udpll5_m2_d20_ckfixed-factor-clockw2=uusim_mux_fck@c40ti,composite-mux-clock("xyz{|}~ @uusim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockR  udpll5_ck@d04ti,omap3-dpll-clock""  $ L 4udpll5_m2_ck@d50ti,divider-clock Puwsgx_gate_fck@b00ti,composite-gate-clock* ucore_d3_ckfixed-factor-clock*2=ucore_d4_ckfixed-factor-clock*2=ucore_d6_ckfixed-factor-clock*2=uomap_192m_alwon_fckfixed-factor-clock&2=ucore_d2_ckfixed-factor-clock*2=usgx_mux_fck@b40ti,composite-mux-clock . @usgx_fckti,composite-clockusgx_ick@b10ti,wait-gate-clockB ucpefuse_fck@a08ti,gate-clock" uts_fck@a08ti,gate-clockD uusbtll_fck@a08ti,wait-gate-clockw uusbtll_ick@a18ti,omap3-interface-clockN ummchs3_ick@a10ti,omap3-interface-clockN ummchs3_fck@a00ti,wait-gate-clock udss1_alwon_fck_3430es2@e00ti,dss-gate-clockxudss_ick_3430es2@e10ti,omap3-dss-interface-clockCuusbhost_120m_fck@1400ti,gate-clockwuusbhost_48m_fck@1400ti,dss-gate-clock4uusbhost_ick@1410ti,omap3-dss-interface-clockCuuart4_fck@1000ti,wait-gate-clockSuclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainjdpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainqd2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsyscQfckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intc H utarget-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss#  Mick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma & 3`ugpio@48310000ti,omap3-gpioH1gpio1@Rb ugpio@49050000ti,omap3-gpioIgpio2Rb ugpio@49052000ti,omap3-gpioI gpio3Rb gpio@49054000ti,omap3-gpioI@ gpio4Rb ugpio@49056000ti,omap3-gpioI`!gpio5Rb ugpio@49058000ti,omap3-gpioI"gpio6Rb serial@4806a000ti,omap3-uartH nHR12txrxuart1lserial@4806c000ti,omap3-uartHnIJ34txrxuart2l]defaultkserial@49020000ti,omap3-uartInJ56txrxuart3li2c@48070000 ti,omap3-i2cH8txrx+i2c1]defaultk'@twl@48H fck ti,twl4030 ]defaultkaudioti,twl4030-audiocodec rtcti,twl4030-rtc bciti,twl4030-bci  vac0watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1--uregulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3**uregulator-vaux4ti,twl4030-vaux4w@w@regulator-vdd1ti,twl4030-vdd1 ' uregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0uregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5uregulator-vusb1v8ti,twl4030-vusb1v8uregulator-vusb3v1ti,twl4030-vusb3v1uregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@uregulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpioRb twl4030-usbti,twl4030-usb !*upwmti,twl4030-pwm5u'pwmledti,twl4030-pwmled5pwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad@Pmadcti,twl4030-madccupower4ti,twl4030-power-idle-osc-offti,twl4030-power-idleui2c@48072000 ti,omap3-i2cH 9txrx+i2c2]defaultki2c@48060000 ti,omap3-i2cH=txrx+i2c3]defaultktsc2004@48 ti,tsc2004H]defaultk n@mailbox@48094000ti,omap3-mailboxmailboxH @:FXdsp j uspi@48098000ti,omap2-mcspiH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3]defaultkspi@4809a000ti,omap2-mcspiH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrxnS]defaultk  mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrxn^6k]default+wlcore@2 ti,wl1273 mmu@480bd400ti,omap2-iommuH mmu_ispummu@5d000000ti,omap2-iommu]mmu_iva "disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< )commontxrx9mcbsp1 txrxfck "disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyssick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?)commontxrxsidetone9mcbsp2mcbsp2_sidetone!"txrxfckick"okay]defaultku mcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZ)commontxrxsidetone9mcbsp3mcbsp3_sidetonetxrxfckick "disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 )commontxrx9mcbsp4txrxfckH "disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR )commontxrx9mcbsp5txrxfck "disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss' fckick+ H1Ymtimer@0ti,omap3430-timerfck%xDtarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss'  fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss'  fckick+ H0@timer@0ti,omap3430-timer_xusbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHM gpmc@6e000000ti,omap3430-gpmcgpmcnrxtx + Rb00,u nand@0,0ti,omap2-nand   micron,mt29f4g16abbda3w-