8`(j((ti,am3517-craneboardti,am3517ti,omap3 +#7TI AM3517 CraneBoard (TMDSEVM3517)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000l/ocp@68000000/can@5c050000cpus+cpu@0arm,cortex-a8pcpu|cpupmu@54000000arm,cortex-a8-pmu|Tdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bus|h +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus| + pinmux@30 ti,omap3-padconfpinctrl-single|08+ +pinmux_tps_pinsH\scm_conf@270sysconsimple-bus|p0+ p0\pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap|dpbias_mmc_omap2430kpbias_mmc_omap2430zw@-\clocks+mcbsp5_mux_fck@68ti,composite-mux-clock|h\mcbsp5_fckti,composite-clock\mcbsp1_mux_fck@4ti,composite-mux-clock|\ mcbsp1_fckti,composite-clock \mcbsp2_mux_fck@4ti,composite-mux-clock |\ mcbsp2_fckti,composite-clock \mcbsp3_mux_fck@68ti,composite-mux-clock |h\mcbsp3_fckti,composite-clock\mcbsp4_mux_fck@68ti,composite-mux-clock |h\mcbsp4_fckti,composite-clock\emac_ick@32cti,am35xx-gate-clock|,\yemac_fck@32cti,gate-clock|, \vpfe_ick@32cti,am35xx-gate-clock|,\zvpfe_fck@32cti,gate-clock|, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock|,\{hsotgusb_fck_am35xx@32cti,gate-clock|,\|hecc_ck@32cti,am35xx-gate-clock|,\}clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single| \+ +aes@480c5000 ti,omap3-aesaes|H PPABtxrxprm@48306000 ti,omap3-prm|H0`@ clocks+virt_16_8m_ck fixed-clockY\osc_sys_ck@d40 ti,mux-clock| @\sys_ck@1270ti,divider-clock|p\sys_clkout1@d70ti,gate-clock| pdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clock\!dpll4_x2_ckfixed-factor-clock corex2_fckfixed-factor-clock!\"wkup_l4_ickfixed-factor-clock\Qcorex2_d3_fckfixed-factor-clock"\rcorex2_d5_fckfixed-factor-clock"\sclockdomainscm@48004000 ti,omap3-cm|H@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clock\Cvirt_12m_ck fixed-clock\virt_13m_ck fixed-clock]@\virt_19200000_ck fixed-clock$\virt_26000000_ck fixed-clock\virt_38_4m_ck fixed-clockI\dpll4_ck@d00ti,omap3-dpll-per-clock| D 0\ dpll4_m2_ck@d48ti,divider-clock ?| H\#dpll4_m2x2_mul_ckfixed-factor-clock#\$dpll4_m2x2_ck@d00ti,gate-clock$| \%omap_96m_alwon_fckfixed-factor-clock%\,dpll3_ck@d00ti,omap3-dpll-core-clock| @ 0\dpll3_m3_ck@1140ti,divider-clock|@\&dpll3_m3x2_mul_ckfixed-factor-clock&\'dpll3_m3x2_ck@d00ti,gate-clock' | \(emu_core_alwon_ckfixed-factor-clock(\esys_altclk fixed-clock\1mcbsp_clks fixed-clock\dpll3_m2_ck@d40ti,divider-clock| @\core_ckfixed-factor-clock\)dpll1_fck@940ti,divider-clock)| @\*dpll1_ck@904ti,omap3-dpll-clock*|  $ @ 4\dpll1_x2_ckfixed-factor-clock\+dpll1_x2m2_ck@944ti,divider-clock+| D\?cm_96m_fckfixed-factor-clock,\-omap_96m_fck@d40 ti,mux-clock-| @\Hdpll4_m3_ck@e40ti,divider-clock  |@\.dpll4_m3x2_mul_ckfixed-factor-clock.\/dpll4_m3x2_ck@d00ti,gate-clock/| \0omap_54m_fck@d40 ti,mux-clock01| @\;cm_96m_d2_fckfixed-factor-clock-\2omap_48m_fck@d40 ti,mux-clock21| @\3omap_12m_fckfixed-factor-clock3\Jdpll4_m4_ck@e40ti,divider-clock |@\4dpll4_m4x2_mul_ckti,fixed-factor-clock40>K\5dpll4_m4x2_ck@d00ti,gate-clock5| K\wdpll4_m5_ck@f40ti,divider-clock ?|@\6dpll4_m5x2_mul_ckti,fixed-factor-clock60>K\7dpll4_m5x2_ck@d00ti,gate-clock7| Kdpll4_m6_ck@1140ti,divider-clock ?|@\8dpll4_m6x2_mul_ckfixed-factor-clock8\9dpll4_m6x2_ck@d00ti,gate-clock9| \:emu_per_alwon_ckfixed-factor-clock:\fclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock)| p\<clkout2_src_mux_ck@d70ti,composite-mux-clock)-;| p\=clkout2_src_ckti,composite-clock<=\>sys_clkout2@d70ti,divider-clock>@| p^mpu_ckfixed-factor-clock?\@arm_fck@924ti,divider-clock@| $emu_mpu_alwon_ckfixed-factor-clock@\gl3_ick@a40ti,divider-clock)| @\Al4_ick@a40ti,divider-clockA| @\Brm_ick@c40ti,divider-clockB| @gpt10_gate_fck@a00ti,composite-gate-clock | \Dgpt10_mux_fck@a40ti,composite-mux-clockC| @\Egpt10_fckti,composite-clockDEgpt11_gate_fck@a00ti,composite-gate-clock | \Fgpt11_mux_fck@a40ti,composite-mux-clockC| @\Ggpt11_fckti,composite-clockFGcore_96m_fckfixed-factor-clockH\mmchs2_fck@a00ti,wait-gate-clock| \mmchs1_fck@a00ti,wait-gate-clock| \i2c3_fck@a00ti,wait-gate-clock| \i2c2_fck@a00ti,wait-gate-clock| \i2c1_fck@a00ti,wait-gate-clock| \mcbsp5_gate_fck@a00ti,composite-gate-clock | \mcbsp1_gate_fck@a00ti,composite-gate-clock | \ core_48m_fckfixed-factor-clock3\Imcspi4_fck@a00ti,wait-gate-clockI| \mcspi3_fck@a00ti,wait-gate-clockI| \mcspi2_fck@a00ti,wait-gate-clockI| \mcspi1_fck@a00ti,wait-gate-clockI| \uart2_fck@a00ti,wait-gate-clockI| \uart1_fck@a00ti,wait-gate-clockI|  \core_12m_fckfixed-factor-clockJ\Khdq_fck@a00ti,wait-gate-clockK| \core_l3_ickfixed-factor-clockA\Lsdrc_ick@a10ti,wait-gate-clockL| \xgpmc_fckfixed-factor-clockLcore_l4_ickfixed-factor-clockB\Mmmchs2_ick@a10ti,omap3-interface-clockM| \mmchs1_ick@a10ti,omap3-interface-clockM| \hdq_ick@a10ti,omap3-interface-clockM| \mcspi4_ick@a10ti,omap3-interface-clockM| \mcspi3_ick@a10ti,omap3-interface-clockM| \mcspi2_ick@a10ti,omap3-interface-clockM| \mcspi1_ick@a10ti,omap3-interface-clockM| \i2c3_ick@a10ti,omap3-interface-clockM| \i2c2_ick@a10ti,omap3-interface-clockM| \i2c1_ick@a10ti,omap3-interface-clockM| \uart2_ick@a10ti,omap3-interface-clockM| \uart1_ick@a10ti,omap3-interface-clockM|  \gpt11_ick@a10ti,omap3-interface-clockM|  \gpt10_ick@a10ti,omap3-interface-clockM|  \mcbsp5_ick@a10ti,omap3-interface-clockM|  \mcbsp1_ick@a10ti,omap3-interface-clockM|  \omapctrl_ick@a10ti,omap3-interface-clockM| \dss_tv_fck@e00ti,gate-clock;|\dss_96m_fck@e00ti,gate-clockH|\dss2_alwon_fck@e00ti,gate-clock|\dummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock| \Ngpt1_mux_fck@c40ti,composite-mux-clockC| @\Ogpt1_fckti,composite-clockNO\aes2_ick@a10ti,omap3-interface-clockM| \wkup_32k_fckfixed-factor-clockC\Pgpio1_dbck@c00ti,gate-clockP| \sha12_ick@a10ti,omap3-interface-clockM| \wdt2_fck@c00ti,wait-gate-clockP| \wdt2_ick@c10ti,omap3-interface-clockQ| \wdt1_ick@c10ti,omap3-interface-clockQ| \gpio1_ick@c10ti,omap3-interface-clockQ| \omap_32ksync_ick@c10ti,omap3-interface-clockQ| \gpt12_ick@c10ti,omap3-interface-clockQ| \gpt1_ick@c10ti,omap3-interface-clockQ| \per_96m_fckfixed-factor-clock,\ per_48m_fckfixed-factor-clock3\Ruart3_fck@1000ti,wait-gate-clockR| \~gpt2_gate_fck@1000ti,composite-gate-clock|\Sgpt2_mux_fck@1040ti,composite-mux-clockC|@\Tgpt2_fckti,composite-clockST\gpt3_gate_fck@1000ti,composite-gate-clock|\Ugpt3_mux_fck@1040ti,composite-mux-clockC|@\Vgpt3_fckti,composite-clockUVgpt4_gate_fck@1000ti,composite-gate-clock|\Wgpt4_mux_fck@1040ti,composite-mux-clockC|@\Xgpt4_fckti,composite-clockWXgpt5_gate_fck@1000ti,composite-gate-clock|\Ygpt5_mux_fck@1040ti,composite-mux-clockC|@\Zgpt5_fckti,composite-clockYZgpt6_gate_fck@1000ti,composite-gate-clock|\[gpt6_mux_fck@1040ti,composite-mux-clockC|@\\gpt6_fckti,composite-clock[\gpt7_gate_fck@1000ti,composite-gate-clock|\]gpt7_mux_fck@1040ti,composite-mux-clockC|@\^gpt7_fckti,composite-clock]^gpt8_gate_fck@1000ti,composite-gate-clock |\_gpt8_mux_fck@1040ti,composite-mux-clockC|@\`gpt8_fckti,composite-clock_`gpt9_gate_fck@1000ti,composite-gate-clock |\agpt9_mux_fck@1040ti,composite-mux-clockC|@\bgpt9_fckti,composite-clockabper_32k_alwon_fckfixed-factor-clockC\cgpio6_dbck@1000ti,gate-clockc|\gpio5_dbck@1000ti,gate-clockc|\gpio4_dbck@1000ti,gate-clockc|\gpio3_dbck@1000ti,gate-clockc|\gpio2_dbck@1000ti,gate-clockc| \wdt3_fck@1000ti,wait-gate-clockc| \per_l4_ickfixed-factor-clockB\dgpio6_ick@1010ti,omap3-interface-clockd|\gpio5_ick@1010ti,omap3-interface-clockd|\gpio4_ick@1010ti,omap3-interface-clockd|\gpio3_ick@1010ti,omap3-interface-clockd|\gpio2_ick@1010ti,omap3-interface-clockd| \wdt3_ick@1010ti,omap3-interface-clockd| \uart3_ick@1010ti,omap3-interface-clockd| \uart4_ick@1010ti,omap3-interface-clockd|\gpt9_ick@1010ti,omap3-interface-clockd| \gpt8_ick@1010ti,omap3-interface-clockd| \gpt7_ick@1010ti,omap3-interface-clockd|\gpt6_ick@1010ti,omap3-interface-clockd|\gpt5_ick@1010ti,omap3-interface-clockd|\gpt4_ick@1010ti,omap3-interface-clockd|\gpt3_ick@1010ti,omap3-interface-clockd|\gpt2_ick@1010ti,omap3-interface-clockd|\mcbsp2_ick@1010ti,omap3-interface-clockd|\mcbsp3_ick@1010ti,omap3-interface-clockd|\mcbsp4_ick@1010ti,omap3-interface-clockd|\mcbsp2_gate_fck@1000ti,composite-gate-clock|\ mcbsp3_gate_fck@1000ti,composite-gate-clock|\mcbsp4_gate_fck@1000ti,composite-gate-clock|\emu_src_mux_ck@1140 ti,mux-clockefg|@\hemu_src_ckti,clkdm-gate-clockh\ipclk_fck@1140ti,divider-clocki|@pclkx2_fck@1140ti,divider-clocki|@atclk_fck@1140ti,divider-clocki|@traceclk_src_fck@1140 ti,mux-clockefg|@\jtraceclk_fck@1140ti,divider-clockj |@secure_32k_fck fixed-clock\kgpt12_fckfixed-factor-clockk\wdt1_fckfixed-factor-clockkipss_ick@a10ti,am35xx-interface-clockL| \rmii_ck fixed-clock\pclk_ck fixed-clock\uart4_ick_am35xx@a10ti,omap3-interface-clockM| uart4_fck_am35xx@a00ti,wait-gate-clockI| dpll5_ck@d04ti,omap3-dpll-clock|  $ L 4t\ldpll5_m2_ck@d50ti,divider-clockl| P\vsgx_gate_fck@b00ti,composite-gate-clock)| \tcore_d3_ckfixed-factor-clock)\mcore_d4_ckfixed-factor-clock)\ncore_d6_ckfixed-factor-clock)\oomap_192m_alwon_fckfixed-factor-clock%\pcore_d2_ckfixed-factor-clock)\qsgx_mux_fck@b40ti,composite-mux-clock mno-pqrs| @\usgx_fckti,composite-clocktu\sgx_ick@b10ti,wait-gate-clockA| \cpefuse_fck@a08ti,gate-clock| \ts_fck@a08ti,gate-clockC| \usbtll_fck@a08ti,wait-gate-clockv| \usbtll_ick@a18ti,omap3-interface-clockM| \mmchs3_ick@a10ti,omap3-interface-clockM| \mmchs3_fck@a00ti,wait-gate-clock| \dss1_alwon_fck_3430es2@e00ti,dss-gate-clockw|K\dss_ick_3430es2@e10ti,omap3-dss-interface-clockB|\usbhost_120m_fck@1400ti,gate-clockv|\usbhost_48m_fck@1400ti,dss-gate-clock3|\usbhost_ick@1410ti,omap3-dss-interface-clockB|\clockdomainscore_l3_clkdmti,clockdomainxyz{|}dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainh~emu_clkdmti,clockdomainidpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainlsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,sysc|H2H2 revsyscPfckick+ H2counter@0ti,omap-counter32k| interrupt-controller@48200000ti,omap3-intc|H \target-module@48056000ti,sysc-omap2ti,sysc|H`H`,H`(revsyscsyss#  Lick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma|  `\gpio@48310000ti,omap3-gpio|H1gpio1gpio@49050000ti,omap3-gpio|Igpio2gpio@49052000ti,omap3-gpio|I gpio3gpio@49054000ti,omap3-gpio|I@ gpio4gpio@49056000ti,omap3-gpio|I`!gpio5gpio@49058000ti,omap3-gpio|I"gpio6serial@4806a000ti,omap3-uart|H !H12txrxuart1lserial@4806c000ti,omap3-uart|H!I34txrxuart2lserial@49020000ti,omap3-uart|I!J56txrxuart3li2c@48070000 ti,omap3-i2c|H8txrx+i2c1'@tps@2d|- ti,tps659105defaultC M^jvregulators+regulator@0|vrtcregulator@1|vioregulator@2|vdd1 kvdd_corezOOregulator@3|vdd2kvdd_shvz2Z2Z\regulator@4|vdd3regulator@5|vdig1regulator@6|vdig2regulator@7|vpllzw@w@regulator@8|vdaczw@w@regulator@9| vaux1zw@w@regulator@10| vaux2zw@w@regulator@11| vaux33regulator@12| vmmcz2Z2Zregulator@13| vbbi2c@48072000 ti,omap3-i2c|H 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2c|H=txrx+i2c3 disabledmailbox@48094000ti,omap3-mailboxmailbox|H @ disableddsp * 5spi@48098000ti,omap2-mcspi|H A+mcspi1@@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspi|H B+mcspi2@ +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspi|H [+mcspi3@ tx0rx0tx1rx1spi@480ba000ti,omap2-mcspi|H 0+mcspi4@FGtx0rx01w@480b2000 ti,omap3-1w|H :hdq1wmmc@4809c000ti,omap3-hsmmc|H Smmc1N=>txrx[htmmc@480b4000ti,omap3-hsmmc|H @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmc|H ^mmc3MNtxrx disabledmmu@480bd400~ti,omap2-iommu|H mmu_isp disabledmmu@5d000000~ti,omap2-iommu|]mmu_iva disabledwdt@48314000 ti,omap3-wdt|H1@ wd_timer2mcbsp@48074000ti,omap3-mcbsp|H@mpu ;< commontxrxmcbsp1 txrxfck disabledtarget-module@480a0000ti,sysc-omap2ti,sysc|H <H @H Drevsyscsyssick+ H  disabledrng@0 ti,omap2-rng| 4mcbsp@49022000ti,omap3-mcbsp|I I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckick disabledmcbsp@49024000ti,omap3-mcbsp|I@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbsp|I`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbsp|H `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamsham|H 0d1Erxtarget-module@48318000ti,sysc-omap2-timerti,sysc|H1H1H1revsyscsyss' fckick+ H1timer@0ti,omap3430-timer|fck% target-module@49032000ti,sysc-omap2-timerti,sysc|I I I revsyscsyss' fckick+ I timer@0ti,omap3430-timer|& timer@49034000ti,omap3430-timer|I@'timer3timer@49036000ti,omap3430-timer|I`(timer4timer@49038000ti,omap3430-timer|I)timer5 timer@4903a000ti,omap3430-timer|I*timer6 timer@4903c000ti,omap3430-timer|I+timer7 timer@4903e000ti,omap3430-timer|I,timer8- timer@49040000ti,omap3430-timer|I-timer9-timer@48086000ti,omap3430-timer|H`.timer10-timer@48088000ti,omap3430-timer|H/timer11-target-module@48304000ti,sysc-omap2-timerti,sysc|H0@H0@H0@revsyscsyss' fckick+ H0@timer@0ti,omap3430-timer|_:usbhstll@48062000 ti,usbhs-tll|H N usb_tll_hsusbhshost@48064000ti,usbhs-host|H@ usb_host_hs+ohci@48064400ti,ohci-omap3|HDLJehci@48064800 ti,ehci-omap|HHMgpmc@6e000000ti,omap3430-gpmcgpmc|nrxtxbn+usb_otg_hs@480ab000ti,omap3-musb|H \]mcdma usb_otg_hs  disableddss@48050000 ti,omap3-dss|H disabled dss_corefck+dispc@48050400ti,omap3-dispc|H dss_dispcfckencoder@4804fc00 ti,omap3-dsi|HH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbi|H disabled dss_rfbifckickencoder@48050c00ti,omap3-venc|H  disabled dss_vencfckssi-controller@48058000 ti,omap3-ssissi disabled|HHsysgddGgdd_mpu+ssi-port@4805a000ti,omap3-ssi-port|HHtxrxCDssi-port@4805b000ti,omap3-ssi-port|HHtxrxEFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hs disabled|\Gmcethernet@5c000000ti,am3517-emac davinci_emacokay|\CDEFd  yickmdio@5c030000ti,davinci_mdio davinci_mdiookay|\/B@+fckserial@4809e000ti,omap3-uartuart4 disabled|H T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-single|H%$+ +can@5c050000ti,am3517-hecc disabled|\\0\ hecchecc-rammbx}target-module@50000000ti,sysc-omap2ti,sysc|Prevfckick+ P@opp-tableoperating-points-v2-ti-cpud\opp50-3000000008?OM^opp100-6000000008#F?OMmemory@80000000pmemory|fixedregulatorregulator-fixedkvbatzLK@LK@\ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3candevice_typeregclocksclock-namesclock-latencyoperating-points-v2interruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockreg-namesti,sysc-sidleti,sysc-maskti,sysc-midleti,syss-mask#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,en-ck32k-xtalvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-compatibleregulator-always-onregulator-boot-on#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-width#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsmultipointnum-epsram-bitsti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqopp-hzopp-microvoltopp-supported-hwopp-suspend