� ��x�8q<(UqFreescale i.MX7 SabreSD Board!fsl,imx7d-sdbfsl,imx7dchosenmemory,memory8��aliases%>gpc@303a0000!fsl,imx7d-gpc80:� �W�D&pgcpgc-power-domain@1&8:==aips-bus@30400000!fsl,aips-bussimple-bus80@@Uadc@30610000!fsl,imx7d-adc80a �b��\adc okayGadc@30620000!fsl,imx7d-adc80b �c��\adc okayGecspi@30630000 !fsl,imx7d-ecspifsl,imx51-ecspi80c �"�  \ipgper  disabledpwm@30660000!fsl,imx7d-pwmfsl,imx27-pwm80f �Q�\ipgperS okay�default�pwm@30670000!fsl,imx7d-pwmfsl,imx27-pwm80g �R�\ipgperS  disabledpwm@30680000!fsl,imx7d-pwmfsl,imx27-pwm80h �S�\ipgperS  disabledpwm@30690000!fsl,imx7d-pwmfsl,imx27-pwm80i �T�\ipgperS  disabledlcdif@30730000 !fsl,imx7d-lcdiffsl,imx28-lcdif80s ��~~\pixaxi okay�default�^displayfudisplay-timingstiming0��a�������)��� ���aips-bus@30800000!fsl,aips-bussimple-bus80�@Uecspi@30820000 !fsl,imx7d-ecspifsl,imx51-ecspi80� ����\ipgper  disabledecspi@30830000 !fsl,imx7d-ecspifsl,imx51-ecspi80� � �\ipgper  disabledecspi@30840000 !fsl,imx7d-ecspifsl,imx51-ecspi80� �!�\ipgper okay�default�  tsc2046@0 !ti,tsc20468B@�default�!D"� 0"=FOXaq� serial@30860000!fsl,imx7d-uartfsl,imx6q-uart80� ����\ipgper okay�default�#��� serial@30890000!fsl,imx7d-uartfsl,imx6q-uart80� ����\ipgper  disabledserial@30880000!fsl,imx7d-uartfsl,imx6q-uart80� ����\ipgper  disabledsai@308a0000�!fsl,imx7d-saifsl,imx6sx-sai80� �_ �����\busmclk1mclk2mclk3�rxtx �$$   disabledsai@308b0000�!fsl,imx7d-saifsl,imx6sx-sai80� �` �����\busmclk1mclk2mclk3�rxtx �$ $   disabledsai@308c0000�!fsl,imx7d-saifsl,imx6sx-sai80� �2 �����\busmclk1mclk2mclk3�rxtx �$ $   disabledcan@30a00000$!fsl,imx7d-flexcanfsl,imx6q-flexcan80� �n���\ipgper  disabledcan@30a10000$!fsl,imx7d-flexcanfsl,imx6q-flexcan80� �o���\ipgper  disabledi2c@30a20000!fsl,imx7d-i2cfsl,imx21-i2c80� �#�� okay�default�%pfuze3000@08!fsl,pfuze30008regulatorssw1a: �`R�����jsw1b: �`R�����jsw2:�`R:���sw3: ��R-P��swbst:LK@RN�0vsnvs:B@R-����vrefddr��vldo1:w@R2Z��vldo2: 5R��vccsd:+|�R2Z��v33:+|�R2Z��vldo3:w@R2Z��vldo4:w@R2Z��i2c@30a30000!fsl,imx7d-i2cfsl,imx21-i2c80� �$�� okay�default�&i2c@30a40000!fsl,imx7d-i2cfsl,imx21-i2c80� �%�� okay�default�'i2c@30a50000!fsl,imx7d-i2cfsl,imx21-i2c80� �&�� okay�default�(wm8960@1a !wlf,wm89608�J\mclkserial@30a60000!fsl,imx7d-uartfsl,imx6q-uart80� ����\ipgper  disabledserial@30a70000!fsl,imx7d-uartfsl,imx6q-uart80� ����\ipgper  disabledserial@30a80000!fsl,imx7d-uartfsl,imx6q-uart80� ����\ipgper okay�default�)��� serial@30a90000!fsl,imx7d-uartfsl,imx6q-uart80� �~���\ipgper  disabledusb@30b10000!fsl,imx7d-usbfsl,imx27-usb80� �+��$*/+;� okayP,usb@30b30000!fsl,imx7d-usbfsl,imx27-usb80� �(��$-/.\hsicehost;�  disabledusbmisc@30b10200m$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc80�++usbmisc@30b30200m$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc80�..usbphynop1!usb-nop-xceiv�� \main_clk**usbphynop3!usb-nop-xceiv�n \main_clk--usdhc@30b40000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc80� ���V� \ipgahbperu okay�default�/ z  �  �usdhc@30b50000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc80� ���V� \ipgahbperu okay"�defaultstate_100mhzstate_200mhz�0�1�2 ���3�usdhc@30b60000!!fsl,imx7d-usdhcfsl,imx6sl-usdhc80� ���V� \ipgahbperu okay"�defaultstate_100mhzstate_200mhz�4�5�6���ׄ��sdma@30bd0000!fsl,imx7d-sdmafsl,imx35-sdma80� ���Z\ipgahb�imx/sdma/sdma-imx7d.bin$$ethernet@30be0000!fsl,imx7d-fecfsl,imx6sx-fec80�$�vwx(�RR�*�"\ipgahbptpenet_clk_refenet_out+ okay�default�7����+���=rgmiiF8Qmdioethernet-phy@0888ethernet-phy@18<<usb@30b20000!fsl,imx7d-usbfsl,imx27-usb80� �*��$9/:;� okayP,ehostusbmisc@30b20200m$!fsl,imx7d-usbmiscfsl,imx6q-usbmisc80�::usbphynop2!usb-nop-xceiv�� \main_clk99ethernet@30bf0000!fsl,imx7d-fecfsl,imx6sx-fec80�$�def(�RR�*�"\ipgahbptpenet_clk_refenet_out+ okay�default�;����+���=rgmiiF<Qpcie@0x33800000!fsl,imx7d-pciesnps,dw-pcie83�@O� bdbiconfig,pci0U�O��@@�l �zvmsi����}|{z�r+v\pciepcie_buspcie_phy�sw�)+��=�>> �pciephyapps okay �?etm@3007d000"!arm,coresight-etm3xarm,primecell80�� �V�@�J \apb_pclkportendpointsAspi4 !spi-gpio�default�B �C  C  C gpio-expander@0!fairchild,74hc595��8 ��??regulator-usb-otg1-vbus!regulator-fixed+usb_otg2_vbus:LK@RLK@ 8D1,,regulator-can2-3v3!regulator-fixed +can2-3v3:2Z�R2Z� 8Cregulator-vref-1v8!regulator-fixed +vref-1v8:w@Rw@regulator-brcm!regulator-fixed 8D1 +brcm_reg�default�E:2Z�R2Z�D @33 #address-cells#size-cellsmodelcompatibledevice_typereggpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6spi0spi1spi2spi3clock-frequencyclock-latencyclocksoperating-pointsarm-supplylinux,phandle#clock-cellsclock-output-namesinterrupt-parentrangesclock-namesslave-moderemote-endpointcpuinterrupts#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsgpio-rangespinctrl-namespinctrl-0fsl,ext-reset-outputstatusfsl,input-selfsl,pinsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitregmapmasklinux,keycodewakeup-source#reset-cells#power-domain-cellspower-supplyvref-supply#pwm-cellsdisplaybits-per-pixelbus-widthnative-modehactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activecs-gpiosspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,pressure-maxti,x-plate-ohmsassigned-clocksassigned-clock-parents#sound-dai-cellsdma-namesdmasregulator-boot-onregulator-always-onregulator-ramp-delaywlf,shared-lrclkuart-has-rtsctsfsl,usbphyfsl,usbmiscphy-clkgate-delay-usvbus-supplyphy_typedr_mode#index-cellscd-gpioswp-gpioskeep-power-in-suspendpinctrl-1pinctrl-2non-removablevmmc-supplyfsl,tuning-stepassigned-clock-rates#dma-cellsfsl,sdma-ram-script-namefsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetreg-namesnum-lanesinterrupt-namesinterrupt-map-maskinterrupt-mapfsl,max-link-speedpower-domainsresetsreset-namesreset-gpioarm,primecell-periphidgpio-sckgpio-mosinum-chipselectsregisters-numberenable-active-highstartup-delay-us