� ����8��( ڨ ',friendlyarm,nanopi-r5srockchip,rk35687FriendlyElec NanoPi R5Saliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000�/serial@fe660000�/serial@fe670000�/serial@fe680000�/serial@fe690000�/serial@fe6a0000�/serial@fe6b0000�/serial@fe6c0000�/serial@fe6d0000�/spi@fe610000�/spi@fe620000�/spi@fe630000�/spi@fe640000�/mmc@fe2b0000�/mmc@fe310000�/ethernet@fe2a0000cpus cpu@0�cpu,arm,cortex-a55�psci%9D cpu@100�cpu,arm,cortex-a55�psci%9D cpu@200�cpu,arm,cortex-a55�psci%9D cpu@300�cpu,arm,cortex-a55�psci%9D opp-table-0,operating-points-v2LDopp-408000000WQ� ^ �� ���0l�@opp-600000000W#�F ^ �� ���0opp-816000000W0�, ^ �� ���0}opp-1104000000WAʹ ^ �� ���0opp-1416000000WTfr ^ �� ���0opp-1608000000W_�" ^�����0opp-1800000000WkI� ^���0opp-1992000000Wv�� ^�0�0�0display-subsystem,rockchip,display-subsystem�firmwarescmi ,arm,scmi-smc��� protocol@14��Dopp-table-1,operating-points-v2DEopp-200000000W ��^ ��opp-300000000W�^ ��opp-400000000Wׄ^ ��opp-600000000W#�F^ ��opp-700000000W)�'^ ��opp-800000000W/�^B@hdmi-sound,simple-audio-card�HDMI�i2s��okaysimple-audio-card,codec�simple-audio-card,cpu�pmu,arm,cortex-a55-pmu0���� psci ,arm,psci-1.0smctimer,arm,armv8-timer0   &xin24m ,fixed-clock=n6Mxin24m�Dxin32k ,fixed-clock=�Mxin32k` jdefault�sram@10f000 ,mmio-sram�� x�sram@0,arm,scmi-shmem�Dsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci��@���satapmaliverxoob _� �sata-phy�� �disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci������satapmaliverxoob `� �sata-phy�� �disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3���@ ����ref_clksuspend_clkbus_clk�host �utmi_wide�����okay ��usb2-phyusb3-phy�usb@fd000000,rockchip,rk3568-dwc3snps,dwc3��@ ����ref_clksuspend_clkbus_clk�host ��usb2-phyusb3-phy �utmi_wide�����okayinterrupt-controller@fd400000 ,arm,gic-v3 ��@�F  ��A"(-Dusb@fd800000 ,generic-ehci��� ������usb�okayusb@fd840000 ,generic-ohci��� ������usb�okayusb@fd880000 ,generic-ehci��� ������usb�okayusb@fd8c0000 ,generic-ohci��� ������usb�okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd���D�io-domains&,rockchip,rk3568-pmu-io-voltage-domain�okay<JXft���syscon@fdc50000��� ,rockchip,rk3568-pipe-grfsysconD�syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd���Dsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsyscon���D�syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsyscon���D�syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsyscon����D�syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsyscon��ʀ�D�clock-controller@fdd00000,rockchip,rk3568-pmucru�����Dclock-controller@fdd20000,rockchip,rk3568-cru���xin24m��� ��G�� ����Di2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c��� .- i2cpclk` jdefault �okayregulator@1c ,tcs,tcs4525�vdd_cpu.BT 5l�0���!Dregulator-state-mem�pmic@20,rockchip,rk809� "�jdefault`#��$�$�$$$$&$2$>$JregulatorsDCDC_REG1 vdd_logic.BXT� l�p�qregulator-state-mem�DCDC_REG2vdd_gpu.XT� l�p�qDFregulator-state-mem�DCDC_REG3vcc_ddr.BXregulator-state-memoDCDC_REG4vdd_npuXT� l�p�qregulator-state-mem�DCDC_REG5vcc_1v8.BTw@lw@Dregulator-state-mem�LDO_REG1vdda0v9_imageT~�l~�DSregulator-state-mem�LDO_REG2 vdda_0v9.BT ��l ��regulator-state-mem�LDO_REG3 vdda0v9_pmu.BT ��l ��regulator-state-memo� ��LDO_REG4 vccio_acodecT2Z�l2Z�Dregulator-state-mem�LDO_REG5 vccio_sdTw@l2Z�Dregulator-state-mem�LDO_REG6 vcc3v3_pmu.BT2Z�l2Z�Dregulator-state-memo�2Z�LDO_REG7 vcca_1v8.BTw@lw@D�regulator-state-mem�LDO_REG8 vcca1v8_pmu.BTw@lw@regulator-state-memo�w@LDO_REG9vcca1v8_imageTw@lw@DTregulator-state-mem�SWITCH_REG1vcc_3v3.BDregulator-state-mem�SWITCH_REG2 vcc3v3_sd.BDXregulator-state-mem�serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart��� t ,baudclkapb_pclk�%%`&jdefault�� �disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��� 0 pwmpclk`'jdefault� �disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��� 0 pwmpclk`(jdefault� �disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm���  0 pwmpclk`)jdefault� �disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm���0 0 pwmpclk`*jdefault� �disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfd���power-controller!,rockchip,rk3568-power-controller� Dpower-domain@7��+�power-domain@8��� �,-.�power-domain@9� ��� �/01�power-domain@10� ���234567�power-domain@11� ��8�power-domain@13� �9�power-domain@14� �:;<�power-domain@15� �=>?@ABCD�gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost���@$()' �jobmmugpugpubus%E��okay�FD�video-codec@fdea0400,rockchip,rk3568-vpu��� ��vdpu�� aclkhclkG� iommu@fdea0800,rockchip,rk3568-iommu���@ � aclkiface��� DGrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga���� Z���aclkhclksclk�&$% coreaxiahb� video-codec@fdee0000,rockchip,rk3568-vepu��� @�� aclkhclkH� iommu@fdee0800,rockchip,rk3568-iommu���@ ?�� aclkiface� DHmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��@ d ����biuciuciu-driveciu-sample!,�р��reset �disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a�� �macirqeth_wake_irq@��������Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref�� stmmaceth�:IJ[JnK� �disabledmdio,snps,dwmac-mdio stmmac-axi-config���DIrx-queues-config�DJqueue0tx-queues-config�DKqueue0vop@fe040000 ��0�@�vopgamma-lut �(�����%aclkhclkdclk_vp0dclk_vp1dclk_vp2L� ��okay,rockchip,rk3568-vop����ports Dport@0� endpoint@2��MDUport@1� port@2� iommu@fe043e00,rockchip,rk3568-iommu ��>�? ��� aclkiface�okayDLdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi�� Dpclk��dphy�N� apb�� �disabledports port@0�port@1�dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi�� Epclk��dphy�O� apb�� �disabledports port@0�port@1�hdmi@fe0a0000,rockchip,rk3568-dw-hdmi��  -(���(�iahbisfrcecrefjdefault `PQR� ����okay STDports port@0�endpoint�UDMport@1�endpoint�VD�qos@fe128000,rockchip,rk3568-qossyscon��� D+qos@fe138080,rockchip,rk3568-qossyscon���� D:qos@fe138100,rockchip,rk3568-qossyscon��� D;qos@fe138180,rockchip,rk3568-qossyscon���� D<qos@fe148000,rockchip,rk3568-qossyscon��� D,qos@fe148080,rockchip,rk3568-qossyscon���� D-qos@fe148100,rockchip,rk3568-qossyscon��� D.qos@fe150000,rockchip,rk3568-qossyscon�� D8qos@fe158000,rockchip,rk3568-qossyscon��� D2qos@fe158100,rockchip,rk3568-qossyscon��� D3qos@fe158180,rockchip,rk3568-qossyscon���� D4qos@fe158200,rockchip,rk3568-qossyscon��� D5qos@fe158280,rockchip,rk3568-qossyscon���� D6qos@fe158300,rockchip,rk3568-qossyscon��� D7qos@fe180000,rockchip,rk3568-qossyscon�� qos@fe190000,rockchip,rk3568-qossyscon�� D=qos@fe190280,rockchip,rk3568-qossyscon��� DAqos@fe190300,rockchip,rk3568-qossyscon�� DBqos@fe190380,rockchip,rk3568-qossyscon��� DCqos@fe190400,rockchip,rk3568-qossyscon�� DDqos@fe198000,rockchip,rk3568-qossyscon��� D9qos@fe1a8000,rockchip,rk3568-qossyscon��� D/qos@fe1a8080,rockchip,rk3568-qossyscon���� D0qos@fe1a8100,rockchip,rk3568-qossyscon��� D1pcie@fe260000,rockchip,rk3568-pcie0��@�&��dbiapbconfig<KJIHG�syspmcmsglegacyerr+(�����$aclk_mstaclk_slvaclk_dbipclkaux�pci5`HWWWWVgv���� �pcie-phy�Tx��� � �@@��pipe �okay �"legacy-interrupt-controller� HDWmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��+@ b ����biuciuciu-driveciu-sample!,�р��reset�okay�������Xjdefault`YZ[\mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��,@ c ����biuciuciu-driveciu-sample!,�р��reset �disabledspi@fe300000 ,rockchip,sfc��0@ exvclk_sfchclk_sfc`]jdefault �disabledmmc@fe310000,rockchip,rk3568-dwcmshc��1 �{}� ��n6(|zy{}corebusaxiblocktimer�okay�, ��jdefault `^_`i2s@fe400000,rockchip,rk3568-i2s-tdm��@ 4�=A�F�qF�q?C9mclk_txmclk_rxhclk�a tx�PQ tx-mrx-m���okayDi2s@fe410000,rockchip,rk3568-i2s-tdm��A 5�EI�F�qF�qGK:mclk_txmclk_rxhclk�aa rxtx�RS tx-mrx-m�jdefault0`bcdefghijklm� �disabledi2s@fe420000,rockchip,rk3568-i2s-tdm��B 6�M�F�qOO;mclk_txmclk_rxhclk�aa txrx�Ttx-m�jdefault`nopq� �disabledi2s@fe430000,rockchip,rk3568-i2s-tdm��C 7SW<mclk_txmclk_rxhclk�aa txrx�UV tx-mrx-m�� �disabledpdm@fe440000,rockchip,rk3568-pdm��D LZYpdm_clkpdm_hclk�a  rx`rstuvwjdefault�Xpdm-m� �disabledspdif@fe460000,rockchip,rk3568-spdif��F f mclkhclk_\�a txjdefault`x� �disableddma-controller@fe530000,arm,pl330arm,primecell��S@ *  apb_pclkAD%dma-controller@fe550000,arm,pl330arm,primecell��U@*  apb_pclkADai2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��Z /HG i2cpclk`yjdefault  �disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��[ 0JI i2cpclk`zjdefault  �disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��\ 1LK i2cpclk`{jdefault  �disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��] 2NM i2cpclk`|jdefault  �disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��^ 3PO i2cpclk`}jdefault �okayrtc@51,haoyu,hym8563�Q"� Mrtcic_32koutjdefault`~Jwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt��` � tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spi��a gRQspiclkapb_pclk�%% txrxjdefault `��  �disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spi��b hTSspiclkapb_pclk�%% txrxjdefault `���  �disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spi��c iVUspiclkapb_pclk�%% txrxjdefault `���  �disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spi��d jXWspiclkapb_pclk�%% txrxjdefault `���  �disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uart��e ubaudclkapb_pclk�%%`�jdefault�� �disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uart��f v# baudclkapb_pclk�%%`�jdefault���okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uart��g w'$baudclkapb_pclk�%%`�jdefault�� �disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uart��h x+(baudclkapb_pclk�%% `�jdefault�� �disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uart��i y/,baudclkapb_pclk�% % `�jdefault�� �disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uart��j z30baudclkapb_pclk�% % `�jdefault�� �disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uart��k {74baudclkapb_pclk�%%`�jdefault�� �disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uart��l |;8baudclkapb_pclk�%%`�jdefault�� �disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uart��m }?<baudclkapb_pclk�%%`�jdefault�� �disabledthermal-zonescpu-thermalLdb�p�tripscpu_alert0�p���passiveD�cpu_alert1�$����passivecpu_crit�s�� �criticalcooling-mapsmap0��0� �������� �������� �������� ��������gpu-thermalLb�p�tripsgpu-threshold�p���passivegpu-target�$����passiveD�gpu-crit�s�� �criticalcooling-mapsmap0�� ����������tsadc@fe710000,rockchip,rk3568-tsadc��q s��f@ �`tsadcapb_pclk������sjinitdefaultsleep`�������okay� D�saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradc��r ]saradcapb_pclk�� saradc-apb �okay 0�pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��nZY pwmpclk`�jdefault� �disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��nZY pwmpclk`�jdefault� �disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n ZY pwmpclk`�jdefault� �disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n0ZY pwmpclk`�jdefault� �disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o]\ pwmpclk`�jdefault� �disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o]\ pwmpclk`�jdefault� �disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o ]\ pwmpclk`�jdefault� �disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o0]\ pwmpclk`�jdefault� �disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p`_ pwmpclk`�jdefault� �disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p`_ pwmpclk`�jdefault� �disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p `_ pwmpclk`�jdefault� �disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p0`_ pwmpclk`�jdefault� �disabledphy@fe830000,rockchip,rk3568-naneng-combphy���"} refapbpipe�"����� <� N� d�okayDphy@fe840000,rockchip,rk3568-naneng-combphy���%~ refapbpipe�%����� <� N� d�okayDphy@fe870000,rockchip,rk3568-csi-dphy���ypclk d��apb� �disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy��� refpclkz d� apb�� �disabledDNmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy��� refpclk{ d� apb�� �disabledDOusb2phy@fe8a0000,rockchip,rk3568-usb2phy���phyclkMclk_usbphy0_480m � o���okayDhost-port d�okay �Dotg-port d�okayDusb2phy@fe8b0000,rockchip,rk3568-usb2phy���phyclkMclk_usbphy1_480m � o���okayhost-port d�okay �Dotg-port d�okayDpinctrl,rockchip,rk3568-pinctrl� �� xD�gpio@fdd60000,rockchip,gpio-bank��� !.  � ��  ��D"gpio@fe740000,rockchip,gpio-bank��t "cd � ��  ��gpio@fe750000,rockchip,gpio-bank��u #ef � ��@  ��D�gpio@fe760000,rockchip,gpio-bank��v $gh � ��`  ��D�gpio@fe770000,rockchip,gpio-bank��w %ij � ���  ��D�pcfg-pull-up �D�pcfg-pull-none �D�pcfg-pull-none-drv-level-1 � �D�pcfg-pull-none-drv-level-2 � �D�pcfg-pull-none-drv-level-3 � �D�pcfg-pull-up-drv-level-1 � �D�pcfg-pull-up-drv-level-2 � �D�pcfg-pull-none-smt � �D�acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ��D cpuebcedpdpemmcemmc-bus8� � � �������D^emmc-clk ��D_emmc-cmd ��D`eth0eth1flashfspifspi-pins` �������D]gmac0gmac0-miim ���D�gmac0-rx-bus20 ����D�gmac0-tx-bus20 � � � �D�gmac0-rgmii-clk ���D�gmac0-rgmii-bus@ �����D�eth-phy0-reset-pin ��D�gmac1gpuhdmitxhdmitxm0-cec ��DRhdmitx-scl ��DPhdmitx-sda ��DQi2c0i2c0-xfer � � �D i2c1i2c1-xfer � � �Dyi2c2i2c2m0-xfer � ��Dzi2c3i2c3m0-xfer ���D{i2c4i2c4m0-xfer � � �D|i2c5i2c5m0-xfer � � �D}i2s1i2s1m0-lrckrx ��Dei2s1m0-lrcktx ��Ddi2s1m0-sclkrx ��Dci2s1m0-sclktx ��Dbi2s1m0-sdi0 � �Dfi2s1m0-sdi1 � �Dgi2s1m0-sdi2 � �Dhi2s1m0-sdi3 ��Dii2s1m0-sdo0 ��Dji2s1m0-sdo1 ��Dki2s1m0-sdo2 � �Dli2s1m0-sdo3 � �Dmi2s2i2s2m0-lrcktx ��Doi2s2m0-sclktx ��Dni2s2m0-sdi ��Dpi2s2m0-sdo ��Dqi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ��Drpdmm0-clk1 ��Dspdmm0-sdi0 � �Dtpdmm0-sdi1 � �Dupdmm0-sdi2 � �Dvpdmm0-sdi3 ��Dwpmicpmic-int ��D#pmupwm0pwm0m0-pins ��D'pwm1pwm1m0-pins ��D(pwm2pwm2m0-pins ��D)pwm3pwm3-pins ��D*pwm4pwm4-pins ��D�pwm5pwm5-pins ��D�pwm6pwm6-pins ��D�pwm7pwm7-pins ��D�pwm8pwm8m0-pins � �D�pwm9pwm9m0-pins � �D�pwm10pwm10m0-pins � �D�pwm11pwm11m0-pins ��D�pwm12pwm12m0-pins ��D�pwm13pwm13m0-pins ��D�pwm14pwm14m0-pins ��D�pwm15pwm15m0-pins ��D�refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ �����DYsdmmc0-clk ��DZsdmmc0-cmd ��D[sdmmc0-det ��D\sdmmc1sdmmc2spdifspdifm0-tx ��Dxspi0spi0m0-pins0 � ���D�spi0m0-cs0 ��Dspi0m0-cs1 ��D�spi1spi1m0-pins0 � ���D�spi1m0-cs0 ��D�spi1m0-cs1 ��D�spi2spi2m0-pins0 ����D�spi2m0-cs0 ��D�spi2m0-cs1 ��D�spi3spi3m0-pins0 � �� �D�spi3m0-cs0 ��D�spi3m0-cs1 ��D�tsadctsadc-shutorg ��D�tsadc-pin ��D�uart0uart0-xfer ���D&uart1uart1m0-xfer � � �D�uart2uart2m0-xfer ���D�uart3uart3m0-xfer ���D�uart4uart4m0-xfer ���D�uart5uart5m0-xfer ���D�uart6uart6m0-xfer ���D�uart7uart7m0-xfer ���D�uart8uart8m0-xfer ���D�uart9uart9m0-xfer ���D�vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2hym8563hym8563-int ��D~usbvcc5v0-usb-host-en ��D�vcc5v0-usb-otg-en ��D�gpio-ledslan1-led-pin ��D�lan2-led-pin ��D�power-led-pin ��D�wan-led-pin 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�D�ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a��*�macirqeth_wake_irq@��������Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref�� stmmaceth�:�J[�n���okay�������sY@ 7output D� Orgmiijdefault`����� X" h ~:��P �< �/mdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22�`�jdefaultD�stmmac-axi-config���D�rx-queues-config�D�queue0tx-queues-config�D�queue0phy@fe820000,rockchip,rk3568-naneng-combphy���| refapbpipe������ <� N� d�okayDchosen �serial2:1500000n8hdmi-con,hdmi-connector�aportendpoint��DVvdd-usbc-regulator,regulator-fixed vdd_usbc.BTLK@lLK@D�vcc3v3-sys-regulator,regulator-fixed vcc3v3_sys.BT2Z�l2Z���D$vcc5v0-sys-regulator,regulator-fixed vcc5v0_sys.BTLK@lLK@��D!vcc3v3-pcie-regulator,regulator-fixed vcc3v3_pcieT2Z�l2Z� � �" � @�!D�vcc5v0-usb-regulator,regulator-fixed vcc5v0_usb.BTLK@lLK@��D�vcc5v0-usb-host-regulator,regulator-fixed � c"jdefault`�vcc5v0_usb_host.BTLK@lLK@��D�vcc5v0-usb-otg-regulator,regulator-fixed � c"jdefault`�vcc5v0_usb_otgTLK@lLK@��D�pcie30-avdd0v9-regulator,regulator-fixedpcie30_avdd0v9.BT ��l ���$pcie30-avdd1v8-regulator,regulator-fixedpcie30_avdd1v8.BTw@lw@�$gpio-leds ,gpio-ledsjdefault`����led-lan1 � �lan � ��led-lan2 � �lan � ��led-power � �power �heartbeat ��led-wan � �wan �� interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1ethernet0device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplybus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosno-sdiono-mmcbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyrockchip,pmugpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfdata-lanesvpcie3v3-supplyclock_in_outphy-handlephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaystdout-pathenable-active-highstartup-delay-uscolorfunctionfunction-enumeratorlinux,default-trigger