� ���\8ڌ( ��T4google,juniper-sku16google,junipermediatek,mt8183 +7Google juniper sku16 board =convertiblealiasesJ/soc/i2c@11007000O/soc/i2c@11011000T/soc/i2c@11009000Y/soc/i2c@1100f000^/soc/i2c@11008000c/soc/i2c@11016000h/soc/i2c@11005000m/soc/i2c@1101a000r/soc/i2c@1101b000w/soc/i2c@11014000|/soc/i2c@11015000�/soc/i2c@11017000�/soc/ovl@14008000�/soc/ovl@14009000�/soc/ovl@1400a000�/soc/rdma@1400b000�/soc/rdma@1400c000�/soc/serial@11002000�/soc/mmc@11230000�/soc/mmc@11240000opp-table-cluster0operating-points-v2�� opp0-793000000�/D8@� ��opp0-910000000�6=�� }��opp0-1014000000��opp0-1417000000�Tu�@� �P�opp0-1508000000�Y�A� A�� opp0-1586000000�^�p�� �6� opp0-1625000000�`ۈ@� � � opp0-1677000000�c��@�5�� opp0-1716000000�fH�f�� opp0-1781000000�j'�@����opp0-1846000000�n���B@�opp0-1924000000�r������opp0-1989000000�v��@���opp-table-cluster1operating-points-v2��$opp1-793000000�/D8@� �`�opp1-910000000�6=�� �opp1-1014000000��opp-689000000�)N@� �P�opp-767000000�-�}�� A�� opp-845000000�2]�@� �6� opp-871000000�3�g�� � � opp-923000000�7���5�� opp-962000000�9V��f�� opp-1027000000�=6������opp-1092000000�A��B@�opp-1144000000�D0����opp-1196000000�GI����ccimediatek,mt8183-cci���cciintermediate�"cpus+cpu-mapcluster0core0$core1$core2$core3$cluster1core0$core1$core2$core3$cpu@0(cpuarm,cortex-a5348psciF�Y���cpuintermediate iT���@����@���!��"�cpu@1(cpuarm,cortex-a5348psciF�Y���cpuintermediate iT���@����@���!��"�cpu@2(cpuarm,cortex-a5348psciF�Y���cpuintermediate iT���@����@���!��"�cpu@3(cpuarm,cortex-a5348psciF�Y���cpuintermediate iT���@����@���!��"�cpu@100(cpuarm,cortex-a7348psciFY#���cpuintermediate$i���@���@��%��"&�cpu@101(cpuarm,cortex-a7348psciFY#���cpuintermediate$i���@���@��%��"&�cpu@102(cpuarm,cortex-a7348psciFY#���cpuintermediate$i���@���@��%��"&�cpu@103(cpuarm,cortex-a7348psciFY#���cpuintermediate$i���@���@��%��"&�idle-statespscicpu-sleeparm,idle-state&=�N�^ �cluster-sleep-0arm,idle-state&=�N�^��cluster-sleep-1arm,idle-state&=�N�^�#l2-cache0cacheo��@�{�!l2-cache1cacheo��@�{�%opp-table-0operating-points-v2��vopp-300000000��� �hopp-320000000��� ��opp-340000000�C�� �<opp-360000000�u*� Ҧopp-380000000��W� �opp-400000000�ׄ� zopp-420000000��� �opp-460000000�k � L�opp-500000000��e� }�opp-540000000� /�� �`opp-580000000�"�� �4opp-620000000�$�s� opp-653000000�&��@� YFopp-698000000�)���� ��opp-743000000�,IG�� �opp-800000000�/�� ��pmu-a53arm,cortex-a53-pmu '�(pmu-a73arm,cortex-a73-pmu '�)psci arm,psci-1.0?smcfixed-factor-clock-13mfixed-factor-clock��*���clk13m�7oscillator fixed-clock������clk26m�*timerarm,armv8-timer '@�   soc+ simple-bus�efuse@8000000%mediatek,mt8183-efusemediatek,efuse4+�okayinterrupt-controller@c000000 arm,gic-v3� '�P4   @ A B �  �'ppi-partitionsinterrupt-partition-0-�(interrupt-partition-1-�)syscon@c530000mediatek,mt8183-mcucfgsyscon4 S��interrupt-controller@c530a80.mediatek,mt8183-sysirqmediatek,mt6577-sysirq�� '4 S �P�cpu-debug@d410000&arm,coresight-cpu-debugarm,primecell4 A�+. �apb_pclk$cpu-debug@d510000&arm,coresight-cpu-debugarm,primecell4 Q�+. �apb_pclk$cpu-debug@d610000&arm,coresight-cpu-debugarm,primecell4 a�+. �apb_pclk$cpu-debug@d710000&arm,coresight-cpu-debugarm,primecell4 q�+. �apb_pclk$cpu-debug@d810000&arm,coresight-cpu-debugarm,primecell4 ��+. �apb_pclk$cpu-debug@d910000&arm,coresight-cpu-debugarm,primecell4 ��+. �apb_pclk$cpu-debug@da10000&arm,coresight-cpu-debugarm,primecell4 ��+. �apb_pclk$cpu-debug@db10000&arm,coresight-cpu-debugarm,primecell4 ��+. �apb_pclk$syscon@10000000 mediatek,mt8183-topckgensyscon4��syscon@10001000 mediatek,mt8183-infracfgsyscon4�6�+syscon@10003000mediatek,mt8183-pericfgsyscon40��gpinctrl@10005000mediatek,mt8183-pinctrl�4P���������DCiocfg0iocfg1iocfg2iocfg3iocfg4iocfg5iocfg6iocfg7iocfg8eintM]i,�� ����uSPI_AP_EC_CS_LSPI_AP_EC_MOSISPI_AP_EC_CLKI2S3_DOUSB_PD_INT_ODLIT6505_HPD_LI2S3_TDM_D3SOC_I2C6_1V8_SCLSOC_I2C6_1V8_SDADPI_D0DPI_D1DPI_D2DPI_D3DPI_D4DPI_D5DPI_D6DPI_D7DPI_D8DPI_D9DPI_D10DPI_D11DPI_HSYNCDPI_VSYNCDPI_DEDPI_CKAP_MSDC1_CLKAP_MSDC1_DAT3AP_MSDC1_CMDAP_MSDC1_DAT0AP_MSDC1_DAT2AP_MSDC1_DAT1OTG_ENDRVBUSDISP_PWMDSI_TELCM_RST_1V8AP_CTS_WIFI_RTSAP_RTS_WIFI_CTSSOC_I2C5_1V8_SCLSOC_I2C5_1V8_SDASOC_I2C3_1V8_SCLSOC_I2C3_1V8_SDASOC_I2C1_1V8_SDASOC_I2C0_1V8_SDASOC_I2C0_1V8_SCLSOC_I2C1_1V8_SCLAP_SPI_H1_MISOAP_SPI_H1_CS_LAP_SPI_H1_MOSIAP_SPI_H1_CLKI2S5_BCKI2S5_LRCKI2S5_DOBOOTBLOCK_EN_LMT8183_KPCOL0SPI_AP_EC_MISOUART_DBG_TX_AP_RXUART_AP_TX_DBG_RXI2S2_MCKI2S2_BCKCLK_5M_WCAMCLK_2M_UCAMI2S2_LRCKI2S2_DISOC_I2C2_1V8_SCLSOC_I2C2_1V8_SDASOC_I2C4_1V8_SCLSOC_I2C4_1V8_SDASCL8SDA8FCAM_PWDN_LI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICI2S_PMICAP_FLASH_WP_LEC_AP_INT_ODLIT6505_INT_ODLH1_INT_OD_LAP_SPI_FLASH_MISOAP_SPI_FLASH_CS_LAP_SPI_FLASH_MOSIAP_SPI_FLASH_CLKDA7219_IRQ�,audiopins��pins-busD�abefYZ[���������audiotdmouton��pins-bus������ �audiotdmoutoff��pins-bus������ ���bt-pins�Bpins-bt-en�x�ec-ap-int-odl�_pins1����h1-int-od-l�Tpins1���i2c0�Epins-bus�RS��i2c1�]pins-bus�QT��i2c2�Qpins-bus�gh�i2c3�[pins-bus�23��i2c4�Gpins-bus�ij�i2c5�apins-bus�01��i2c6�Dpins-bus�  mmc0-pins-default�kpins-cmd-dat$�{�}�~��z���pins-clk�|� pins-rst��� mmc0-pins-uhs�lpins-cmd-dat$�{�}�~��z���pins-clk�|� pins-ds��� pins-rst����mmc1-pins-default�opins-cmd-dat� "!�� pins-clk�� mmc1-pins-uhs�ppins-cmd-dat� "!��� pins-clk�� �panel-pins-defaultpanel-reset�-��pwm0-pin-default�Zpins1��$�pins2�+scp�6pins-scp-uart�npspi0�Spins-spi�UVWXspi1�\pins-spi�����spi2�^pins-spi �pins-spi-mi�^ spi3�`pins-spi�spi4�cpins-spi�spi5�dpins-spi� uart0-pins-default�?pins-rx�_��pins-tx�`uart1-pins-default�@pins-rx�y��pins-tx�spins-rts�/0pins-cts�.�uart1-pins-sleep�Apins-rx�y��pins-tx�spins-rts�/0pins-cts�.�wifi-pins-pwrseq��pins-wifi-enable�w�wifi-pins-wakeup��pins-wifi-wakeup�q�pp1200-mipibrdg-en��pins1�6�pp1800-lcd-en��pins1�$�pp3300-panel-pins��panel-3v3-enable�#�ppvarp-lcd-enpins1�B�ppvarn-lcd-enpins1���anx7625-pins�Hpins1�-I�pins2���touchscreen-pins�Ftouch-int-odl����touch-rst-l��$trackpad-pins�Rtrackpad-int��vddio-mipibrdg-en��pins1�%�volume-button-pins��voldn-btn-odl���volup-btn-odl���ts3a227e_pins�bpins1����syscon@10006000)mediatek,mt8183-scpsyssysconsimple-mfd4`power-controller!mediatek,mt8183-power-controller+>�Ypower-domain@04� +/+7�audioaudio1audio2>power-domain@14R+>power-domain@24��mfg+>d-power-domain@34+>d.power-domain@44>power-domain@54>power-domain@64R+>power-domain@74X�////////// 5�mmmm-0mm-1mm-2mm-3mm-4mm-5mm-6mm-7mm-8mm-9R+r0+>power-domain@84@�11 11111.�camcam-0cam-1cam-2cam-3cam-4cam-5cam-6R+r0>power-domain@94 �"2 2�ispisp-0isp-1R+r0>power-domain@104 r0>power-domain@114 r0>power-domain@124 @�&#333333-�vpuvpu1vpu-0vpu-1vpu-2vpu-3vpu-4vpu-5R+r0+>power-domain@134 �$�vpu2R+>power-domain@144�%�vpu3R+>watchdog@10007000mediatek,mt8183-wdt4p6�isyscon@1000c000"mediatek,mt8183-apmixedsyssyscon4���Xpwrap@1000d000mediatek,mt8183-pwrap4�Cpwrap ���)+ �spiwrappmicmediatek,mt6358� ,���mt6358codecmediatek,mt6358-sound�4mt6358regulatormediatek,mt6358-regulatorbuck_vdram1�vdram1�� ��L�0��"buck_vcore�vcore�� ����j��"buck_vpa�vpa�� �7����P��"buck_vproc11�vproc11�� ����j��"�&buck_vproc12�vproc12�� ����j��"�buck_vgpu�vgpu�� � ���j��":-Q���.buck_vs2�vs2�� ��L�0��buck_vmodem�vmodem�� ����j��"buck_vs1�vs1�B@�'{l�0��ldo_vdram2�vdram2� '��w@� �ldo_vsim1�vsim1�)2��)2��ldo_vibr�vibr�O��2Z��<ldo_vrf12regulator-fixed�vrf12�O��O��xldo_vio18regulator-fixed�vio18�w@�w@� ��nldo_vusb�vusb�-���/M`��hldo_vcamioregulator-fixed�vcamio�w@�w@�Eldo_vcamd�vcamd� ���w@�Eldo_vcn18regulator-fixed�vcn18�w@�w@�ldo_vfe28regulator-fixed�vfe28�*���*���ldo_vsram_proc11 �vsram_proc11�� ����j��ldo_vcn28regulator-fixed�vcn28�*���*���ldo_vsram_others �vsram_others�� ����j��ldo_vsram_gpu �vsram_gpu� �P�B@�j��:.Q���-ldo_vxo22regulator-fixed�vxo22�!���!���xldo_vefuse�vefuse������ldo_vaux18regulator-fixed�vaux18�w@�w@�ldo_vmch�vmch�,@ �2Z��<ldo_vbif28regulator-fixed�vbif28�*���*���ldo_vsram_proc12 �vsram_proc12�� ����j��ldo_vcama1�vcama1�w@�-���Eldo_vemc�vemc�,@ �2Z��<�mldo_vio28regulator-fixed�vio28�*���*���ldo_va12regulator-fixed�va12�O��O��ldo_vrf18regulator-fixed�vrf18�w@�w@�xldo_vcn33_bt �vcn33_bt�2Z��5g��ldo_vcn33_wifi �vcn33_wifi�2Z��5g��ldo_vcama2�vcama2�w@�-���Eldo_vmc�vmc�w@�2Z��<ldo_vldo28�vldo28�*���-���ldo_vaud28regulator-fixed�vaud28�*���*����4ldo_vsim2�vsim2�)2��)2��rtcmediatek,mt6358-rtckeysmediatek,mt6358-keyspowernt}homenfkeyboard@10010000mediatek,mt6779-keypad4 ���*�kpd �disabledscp@10500000mediatek,mt8183-scp 4P\�� Csramcfg ���+�main�5�okay�mediatek/mt8183/scp.img�default�6cros_ecgoogle,cros-ec-rpmsg�cros-ec-rpmsgtimer@10017000,mediatek,mt8183-timermediatek,mt6765-timer4p ���7iommu@10205000mediatek,mt8183-m4u4 P ���89:;<=>��xmailbox@10238000mediatek,mt8183-gce4#�@ ����+�gce�wauxadc@11001000.mediatek,mt8183-auxadcmediatek,mt8173-auxadc4�+#�main��okay�Wserial@11002000*mediatek,mt8183-uartmediatek,mt6577-uart4  �[ �*+ �baudbus�okay�default�?serial@11003000*mediatek,mt8183-uartmediatek,mt6577-uart40 �*+ �baudbus�okay�defaultsleep�@ A\,ybluetooth�default�B�okayqcom,qca6174-bt +,x�C�nvm_00440302_i2s.binserial@11004000*mediatek,mt8183-uartmediatek,mt6577-uart4@ �] �*+ �baudbus �disabledi2c@11005000mediatek,mt8183-i2c 4P� �W�+W+* �maindma�+�okay�default�D���i2c@11007000mediatek,mt8183-i2c 4p�� �Q�+ +* �maindma�+�okay�default�E��touchscreen@10elan,ekth35004�default�F ,� 8,�i2c@11008000mediatek,mt8183-i2c 4�� �R�+ +*+G �maindmaarb�+�okay�default�G���anx7625@58analogix,anx76254X�default�HD +,- 8,IPI]JjK+port@04endpointwL�zport@14endpointwM�Paux-buspanel edp-panel�N�OportendpointwP�Mi2c@11009000mediatek,mt8183-i2c 4��� �S�+ +*+I �maindmaarb�+�okay�default�Q��trackpad@15elan,ekth30004�default�R ,}trackpad@2c hid-over-i2c4,� �default�R ,}spi@1100a000mediatek,mt8183-spi+4� �x�6+�parent-clksel-clkspi-clk�okay�default�S� �,Vcr50@0 google,cr504�B@�default�T ,��svs@1100b000mediatek,mt8183-svs4� ��+ �main�UV(�svs-calibration-datat-calibration-datathermal@1100b000�mediatek,mt8183-thermal4��+ +# �thermauxadc+ �LW&X�V�calibration-data�}pwm@1100e000mediatek,mt8183-disp-pwm4� ��:YH�+5�mainmm�okay�default�Z��pwm@11006000mediatek,mt8183-pwm4`H0�++++++�topmainpwm1pwm2pwm3pwm4i2c@1100f000mediatek,mt8183-i2c 4�� �T�+ +* �maindma�+�okay�default�[���spi@11010000mediatek,mt8183-spi+4 �|�6+8�parent-clksel-clkspi-clk�okay�default�\�flash@0winbond,w25q64dwjedec,spi-nor4�}x@i2c@11011000mediatek,mt8183-i2c 4�� �U�+9+* �maindma�+�okay�default�]���spi@11012000mediatek,mt8183-spi+4  ���6+;�parent-clksel-clkspi-clk�okay�default�^�cros-ec@0google,cros-ec-spi4�-�� ,���default�_i2c-tunnelgoogle,cros-ec-i2c-tunnelS+sbs-battery@bsbs,sbs-battery4 eyextcon0google,extcon-usbc-cros-ec�typecgoogle,cros-ec-typec+connector@0usb-c-connector4�dual�host�sinkkeyboard-controllergoogle,cros-ec-keyb�� �D;<=>?@A B CD}0Y1 d"#(  \V |})  � + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ipwmgoogle,cros-ec-pwmH �disabledspi@11013000mediatek,mt8183-spi+40 ���6+<�parent-clksel-clkspi-clk �disabled�default�`�i2c@11014000mediatek,mt8183-i2c 4@�� ���+H+*+G �maindmaarb�+ �disabledi2c@11015000mediatek,mt8183-i2c 4P� ���+J+*+I �maindmaarb�+ �disabledi2c@11016000mediatek,mt8183-i2c 4`� �V�+D+*+E �maindmaarb�+�okay�default�a���ts3a227e@3b�default�b ti,ts3a227e4; ,���okay��i2c@11017000mediatek,mt8183-i2c 4p�� ���+F+*+E �maindmaarb�+ �disabledspi@11018000mediatek,mt8183-spi+4� ���6+K�parent-clksel-clkspi-clk �disabled�default�c�spi@11019000mediatek,mt8183-spi+4� ���6+L�parent-clksel-clkspi-clk �disabled�default�d�i2c@1101a000mediatek,mt8183-i2c 4��� �X�+b+* �maindma�+ �disabledi2c@1101b000mediatek,mt8183-i2c 4�� �Y�+c+* �maindma�+ �disabledusb@11201000#mediatek,mt8183-mtu3mediatek,mtu3 4 . > Cmacippc �Hef�+=+Z�sys_ckref_ck g e+��okay+host}3husb@11200000'mediatek,mt8183-xhcimediatek,mtk-xhci4 Cmac �I�+=+Z�sys_ckref_ck�okay+3hhub@1 usb5e3,6104audio-controller@11220000 mediatek,mt8183-audiosyssyscon4"��jmt8183-afe-pcmmediatek,mt8183-audio ��i Aaudiosys:YD�jjjjj jjjjj j j j jj+/+7  0HLKOtuvwxyz{|}~*w�aud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adc_adda6_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_i2s1_bclk_swaud_i2s2_bclk_swaud_i2s3_bclk_swaud_i2s4_bclk_swaud_tdm_clkaud_tml_clkaud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_aud_intbustop_syspll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_clk26m_clk��mmc@11230000mediatek,mt8183-mmc 4#� �M�++�sourcehclksource_cg�okay�defaultstate_uhs�k lM� ��Wix����(�m�n��U�mmc@11240000mediatek,mt8183-mmc 4$� �N� ++(�sourcehclksource_cg�okay�defaultstate_uhs�o p�q�r sM� ��   , :} P� ]�� �V+qca-wifi@1 qcom,ath10k4 dGO_JUNIPERdsi-phy@11e50000mediatek,mt8183-mipi-tx4��X� � �mipi_tx0_pll�t�calibration-data�okay�yefuse@11f10000%mediatek,mt8183-efusemediatek,efuse4�+calib@1804� �Vcalib@1904� �tcalib@5804�d�Ut-phy@11f40000.mediatek,mt8183-tphymediatek,generic-tphy-v2+���okayusb-phy@04�*�ref � ��okay�eusb-phy@7004 �*�ref ��okay�fsyscon@13000000mediatek,mt8183-mfgcfgsyscon4�:Y�ugpu@13040000'mediatek,mt8183b-maliarm,mali-bifrost4@$� �jobmmugpu�u:YYY �core0core1core2v �.syscon@14000000mediatek,mt8183-mmsyssyscon4�6 �ww �w�/dma-controller0@14001000mediatek,mt8183-mdp3-rdma4 �w �:Y�/ / x �ww mdp3-rsz0@14003000mediatek,mt8183-mdp3-rsz40 �w0 ��/mdp3-rsz1@14004000mediatek,mt8183-mdp3-rsz4@ �w@ ��/dma-controller@14005000mediatek,mt8183-mdp3-wrot4P �wP �!:Y�/ x mdp3-wdma@14006000mediatek,mt8183-mdp3-wdma4` �w` �":Y�/) xovl@14008000mediatek,mt8183-disp-ovl4� ��:Y�/ x �w�ovl@14009000mediatek,mt8183-disp-ovl-2l4� ��:Y�/ x �w�ovl@1400a000mediatek,mt8183-disp-ovl-2l4� ��:Y�/ x �w�rdma@1400b000mediatek,mt8183-disp-rdma4� ��:Y�/ x  �w�rdma@1400c000mediatek,mt8183-disp-rdma4� ��:Y�/ x  �w�color@1400e0006mediatek,mt8183-disp-colormediatek,mt8173-disp-color4� ��:Y�/ �w�ccorr@1400f000mediatek,mt8183-disp-ccorr4� ��:Y�/ �w�aal@14010000mediatek,mt8183-disp-aal4 ��:Y�/ �wgamma@14011000mediatek,mt8183-disp-gamma4 ��:Y�/ �wdither@14012000mediatek,mt8183-disp-dither4  ��:Y�/ �w dsi@14014000mediatek,mt8183-dsi4@ ��:Y�// y�enginedigitalhs/y +dphy�okayportsportendpointwz�Lmutex@14016000mediatek,mt8183-disp-mutex4` ��:Y ��� �w`larb@14017000mediatek,mt8183-smi-larb4pr0�//:Y�apbsmi�8smi@14019000mediatek,mt8183-smi-common4� �////�apbsmigals0gals1:Y�0mdp3-ccorr@1401c000mediatek,mt8183-mdp3-ccorr4� �w� �1�/+syscon@15020000mediatek,mt8183-imgsyssyscon4��2larb@15021000mediatek,mt8183-smi-larb4r0�2 2 / �apbsmigals:Y �=larb@1502f000mediatek,mt8183-smi-larb4�r0�22/  �apbsmigals:Y �:syscon@16000000mediatek,mt8183-vdecsyssyscon4��{larb@16010000mediatek,mt8183-smi-larb4r0�{{�apbsmi:Y �9syscon@17000000mediatek,mt8183-vencsyssyscon4��|larb@17010000mediatek,mt8183-smi-larb4r0�||�apbsmi:Y �<venc_jpg@17030000+mediatek,mt8183-jpgencmediatek,mtk-jpgenc4 �� x�x�:Y �|�jpgencsyscon@19000000 mediatek,mt8183-ipu_connsyscon4��3syscon@19010000mediatek,mt8183-ipu_adlsyscon4�syscon@19180000!mediatek,mt8183-ipu_core0syscon4�syscon@19280000!mediatek,mt8183-ipu_core1syscon4(�syscon@1a000000mediatek,mt8183-camsyssyscon4��1larb@1a001000mediatek,mt8183-smi-larb4r0�11/ �apbsmigals:Y�>larb@1a002000mediatek,mt8183-smi-larb4 r0�1 1 / �apbsmigals:Y�;thermal-zonescpu-thermal 5d K� Y} i�tripstrip-point0 { � ��Epassivetrip-point1 {8� ��Epassive�~cpu-crit {�8 �� Ecriticalcooling-mapsmap0 �~0 ��������������������������������� � map1 �~0 ��������������������������������� �tzts1 5 K Y} i�tripscooling-mapstzts2 5 K Y} i�tripscooling-mapstzts3 5 K Y} i�tripscooling-mapstzts4 5 K Y} i�tripscooling-mapstzts5 5 K Y} i�tripscooling-mapstztsABB 5 K Y} i�tripscooling-mapstboard1 K� 5 Ytboard2 K� 5 Y�chosen �serial0:115200n8backlight_lcd0pwm-backlight ��� �� +,� �� �� �@�okay�Omemory@40000000(memory4@�oscillator1 fixed-clock����clk32k�Cregulator0regulator-fixed �it6505_pp18�w@�w@ ,� regulator1regulator-fixed �lcd_pp3300�2Z��2Z� regulator2regulator-fixed �bl_pp5000�LK@�LK@ ��regulator3regulator-fixed �mmc1_power�2Z��2Z��qregulator4regulator-fixed�mmc1_io�w@�w@�rregulator5regulator-fixed �pp1800_alw �w@�w@regulator6regulator-fixed �pp3300_alw �2Z��2Z�reserved-memory+�memory@50000000shared-dma-pool4P� 0�5mt8183-sound 7�'�defaultaud_tdm_out_onaud_tdm_out_off�� � I��okay S�(mediatek,mt8183_mt6358_ts3a227_max98357bt-sco linux,bt-scowifi-pwrseqmmc-pwrseq-simple�default�� 8,w�swifi-wakeup gpio-keys�default��button-wowlan jWake on WiFi 2,q p�}thermal-sensor1generic-adc-thermal� {W �sensor-channel� ����x���'.:��N la�u0���7�@���{�P(����`���ap/$�8��L�_��s���y�(h��Z�8N��C�H;�thermal-sensor2generic-adc-thermal� {W �sensor-channel� ����x���'.:��N la�u0���7�@���{�P(����`���ap/$�8��L�_��s���y�(h��Z�8N��C�H;��pp1200-mipibrdgregulator-fixed�pp1200_mipibrdg�default��   ,6�Ipp1800-mipibrdgregulator-fixed�pp1800_mipibrdg�default��   ,$�Jpp3300-panelregulator-fixed �pp3300_panel�2Z��2Z��default��   ,#�Nvddio-mipibrdgregulator-fixed�vddio_mipibrdg�default��   ,%�Kvolume-buttons gpio-keys�default��button-volume-down jVolume Down pr �d 2,button-volume-up jVolume Up ps �d 2,max98357amaxim,max98357a �,� compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typei2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11ovl0ovl-2l0ovl-2l1rdma0rdma1serial0mmc0mmc1opp-sharedphandleopp-hzopp-microvoltrequired-oppsclocksclock-namesoperating-points-v2proc-supplycpudevice_typeregenable-methodcapacity-dmips-mhzcpu-idle-statesdynamic-power-coefficienti-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterrupts#clock-cellsclock-divclock-multclock-output-namesclock-frequencyrangesstatus#interrupt-cellsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxdrive-strengthinput-enablebias-pull-downoutput-lowbias-pull-upmediatek,pull-up-advmediatek,drive-strength-advbias-disablemediatek,pull-down-advoutput-highoutput-enable#power-domain-cellsmediatek,infracfgdomain-supplymediatek,smimediatek,dmic-modeAvdd-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-always-onregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadlinux,keycodeswakeup-sourcememory-regionfirmware-namepinctrl-namespinctrl-0mediatek,rpmsg-namemediatek,larbs#iommu-cells#mbox-cells#io-channel-cellspinctrl-1interrupts-extendedenable-gpiosreset-gpiospanel_flagsvdd10-supplyvdd18-supplyvdd33-supplyremote-endpointpower-supplybacklighthid-descr-addrmediatek,pad-selectcs-gpiosspi-max-frequencynvmem-cellsnvmem-cell-names#thermal-sensor-cellsresetsmediatek,auxadcmediatek,apmixedsyspower-domains#pwm-cellsgoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countgoogle,usb-port-idpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapphysmediatek,syscon-wakeupdr_modevusb33-supplyreset-namesbus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-parentsnon-removablemmc-pwrseqcap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104keep-power-in-suspendcap-sdio-irqno-mmcqcom,ath10k-calibration-variant#phy-cellsmediatek,discthinterrupt-namespower-domain-namesmali-supplymboxesmediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,rdma-fifo-sizephy-namespolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionstdout-pathpwmsbrightness-levelsnum-interpolated-stepsdefault-brightness-levelgpioenable-active-highregulator-boot-onno-mapmediatek,platformpinctrl-2mediatek,headset-codeclabellinux,codeio-channelsio-channel-namestemperature-lookup-tabledebounce-intervalsdmode-gpios