� ��2>80(&/� ,Spreadtrum SP9863A-1H10 Board2sprd,sp9863a-1h10sprd,sc9863asoc 2simple-bus =syscon@20e00000'2sprd,sc9863a-glbregssysconsimple-mfdD �@ = �@apahb-gate2sprd,sc9863a-apahb-gateD HU+syscon@402b0000'2sprd,sc9863a-glbregssysconsimple-mfdD@+@ =@+@pmu-gate2sprd,sc9863a-pmu-gateD]dext-26mHsyscon@402e0000'2sprd,sc9863a-glbregssysconsimple-mfdD@.@ =@.@aonapb-gate2sprd,sc9863a-aonapb-gateDHsyscon@40353000'2sprd,sc9863a-glbregssysconsimple-mfdD@500 =@500pll2sprd,sc9863a-pllD]dext-26mHsyscon@40359000'2sprd,sc9863a-glbregssysconsimple-mfdD@5�0 =@5�0mpll2sprd,sc9863a-mpllDHsyscon@4035c000'2sprd,sc9863a-glbregssysconsimple-mfdD@5�0 =@5�0rpll2sprd,sc9863a-rpllD]dext-26mHU,syscon@40363000'2sprd,sc9863a-glbregssysconsimple-mfdD@600 =@600dpll2sprd,sc9863a-dpllDHsyscon@60800000'2sprd,sc9863a-glbregssysconsimple-mfdD`� =`�0mm-gate2sprd,sc9863a-mm-gateDHsyscon@71300000'2sprd,sc9863a-glbregssysconsimple-mfdDq0@ =q0@apapb-gate2sprd,sc9863a-apapb-gateD]dext-26mHapb@70000000 2simple-bus =pserial@0#2sprd,sc9863a-uartsprd,sc9836-uartD p]{okayserial@100000#2sprd,sc9863a-uartsprd,sc9836-uartD p]{okayserial@200000#2sprd,sc9863a-uartsprd,sc9836-uartD  p] {disabledserial@300000#2sprd,sc9863a-uartsprd,sc9836-uartD0 p] {disabledserial@400000#2sprd,sc9863a-uartsprd,sc9836-uartD@ p] {disabledinterrupt-controller@14000000 2arm,gic-v3� =��� D p Uclock-controller@215000002sprd,sc9863a-ap-clkD!P]dext-32kext-26mHclock-controller@402d00002sprd,sc9863a-aon-clkD@-] dext-26mrco-100mext-32kext-4mHU*clock-controller@609000002sprd,sc9863a-mm-clkD`�Hfunnel@10001000+2arm,coresight-dynamic-funnelarm,primecellD] dapb_pclkout-portsportendpoint�Uin-portsportendpoint�Uetb@10003000 2arm,coresight-tmcarm,primecellD0] dapb_pclkin-portsportendpoint�Ufunnel@12001000+2arm,coresight-dynamic-funnelarm,primecellD] dapb_pclkout-portsportendpoint� Uin-ports port@0Dendpoint� Uport@1Dendpoint� Uport@2Dendpoint� Uport@3Dendpoint� U!etf@12002000 2arm,coresight-tmcarm,primecellD ] dapb_pclkout-portsportendpoint�Uin-portportendpoint�U etf@12003000 2arm,coresight-tmcarm,primecellD0] dapb_pclkout-portsportendpoint�Uin-portsportendpoint�Ufunnel@12004000+2arm,coresight-dynamic-funnelarm,primecellD@] dapb_pclkout-portsportendpoint�Uin-ports port@0Dendpoint�Uport@1Dendpoint�Ufunnel@12005000+2arm,coresight-dynamic-funnelarm,primecellDP] dapb_pclkout-portsportendpoint�Uin-ports port@0Dendpoint�U#port@1Dendpoint�U%port@2Dendpoint�U'port@3Dendpoint�U)etm@13040000"2arm,coresight-etm4xarm,primecellD�] dapb_pclkout-portsportendpoint�U etm@13140000"2arm,coresight-etm4xarm,primecellD�] dapb_pclkout-portsportendpoint�U etm@13240000"2arm,coresight-etm4xarm,primecellD$�] dapb_pclkout-portsportendpoint�U etm@13340000"2arm,coresight-etm4xarm,primecellD4� ] dapb_pclkout-portsportendpoint�!U etm@13440000"2arm,coresight-etm4xarm,primecellDD�"] dapb_pclkout-portsportendpoint�#Uetm@13540000"2arm,coresight-etm4xarm,primecellDT�$] dapb_pclkout-portsportendpoint�%Uetm@13640000"2arm,coresight-etm4xarm,primecellDd�&] dapb_pclkout-portsportendpoint�'Uetm@13740000"2arm,coresight-etm4xarm,primecellDt�(] dapb_pclkout-portsportendpoint�)Uap-ahb 2simple-bus =sdio@203000002sprd,sdhci-r11D 0 p9 dsdioenable]*+�*�,!sdio@206000002sprd,sdhci-r11D ` p< dsdioenable]*!+�*!�,(6<ext-26m 2fixed-clockHM���]ext-26mUext-32k 2fixed-clockHM�]ext-32kUext-4m 2fixed-clockHM= ]ext-4mUrco-100m 2fixed-clockHM�� ]rco-100mUcpus cpu-mapcluster0core0�core1�core2�core3� core4�"core5�$core6�&core7�(cpu@0pcpu2arm,cortex-a55D|psci�-Ucpu@100pcpu2arm,cortex-a55D|psci�-Ucpu@200pcpu2arm,cortex-a55D|psci�-Ucpu@300pcpu2arm,cortex-a55D|psci�-U cpu@400pcpu2arm,cortex-a55D|psci�-U"cpu@500pcpu2arm,cortex-a55D|psci�-U$cpu@600pcpu2arm,cortex-a55D|psci�-U&cpu@700pcpu2arm,cortex-a55D|psci�-U(idle-states�pscicore-pd2arm,idle-state�����'��U-psci 2arm,psci-0.2�smctimer2arm,armv8-timer0p   pmu2arm,armv8-pmuv3`p��������aliases/soc/apb@70000000/serial@0  /soc/apb@70000000/serial@100000memory@80000000pmemoryD��chosenserial1:115200n8 earlycon interrupt-parent#address-cells#size-cellsmodelcompatiblerangesreg#clock-cellsphandleclocksclock-namesinterruptsstatus#interrupt-cellsredistributor-stride#redistributor-regionsinterrupt-controllerremote-endpointcpuassigned-clocksassigned-clock-parentsbus-widthno-sdiono-mmcnon-removableno-sdcap-mmc-hw-resetclock-frequencyclock-output-namesdevice_typeenable-methodcpu-idle-statesentry-methodentry-latency-usexit-latency-usmin-residency-uslocal-timer-stoparm,psci-suspend-paramserial0serial1stdout-pathbootargs