U8M(MHSedgeble,neural-compute-module-2-ioedgeble,neural-compute-module-2rockchip,rv1126&7Edgeble Neu2 IO Boardaliases=/i2c@ff3f0000B/i2c@ff400000G/serial@ff560000O/serial@ff410000W/serial@ff570000_/serial@ff580000g/serial@ff590000o/serial@ff5a0000w/mmc@ffc50000cpuscpu@f00|cpuarm,cortex-a7pscicpu@f01|cpuarm,cortex-a7pscicpu@f02|cpuarm,cortex-a7pscicpu@f03|cpuarm,cortex-a7psciarm-pmuarm,cortex-a7-pmu0{|}~psci arm,psci-1.0smctimerarm,armv7-timer0   n6display_subsystemrockchip,display-subsystemoscillator fixed-clockn6xin24m#syscon@fe000000&rockchip,rv1126-grfsysconsimple-mfd"syscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfdio-domains&rockchip,rv1126-pmu-io-voltage-domainokay  + 9 G Uc q qos@fe860000rockchip,rv1126-qossyscon qos@fe860080rockchip,rv1126-qossyscon qos@fe860200rockchip,rv1126-qossyscon qos@fe86c000rockchip,rv1126-qossyscon qos@fe8a0000rockchip,rv1126-qossyscon qos@fe8a0080rockchip,rv1126-qossyscon qos@fe8a0100rockchip,rv1126-qossyscon qos@fe8a0180rockchip,rv1126-qossyscon interrupt-controller@feff0000 arm,gic-400  @ `   power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd>power-controller!rockchip,rv1126-power-controller0power-domain@158ruv power-domain@16opower-domain@10 PZ[i2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c?  ! i2cpclkdefaultokaypmic@20rockchip,rk809 & rk808-clkout1rk808-clkout2default .:FR^jv (regulatorsDCDC_REG1 vdd_npu_vepu ~qregulator-state-mem+DCDC_REG2vdd_arm pqregulator-state-mem+DCDC_REG3vcc_ddrregulator-state-memDDCDC_REG4 vcc3v3_sys2Z2Z regulator-state-memD\2ZDCDC_REG5 vcc_buck5!!regulator-state-memD\!LDO_REG1vcc_0v8 5 5regulator-state-mem+LDO_REG2 vcc1v8_pmuw@w@ regulator-state-memD\w@LDO_REG3 vcc0v8_pmu 5 5regulator-state-memD\ 5LDO_REG4vcc_1v8w@w@ regulator-state-memD\w@LDO_REG5 vcc_dovddw@w@regulator-state-mem+LDO_REG6 vcc_dvddOOregulator-state-mem+LDO_REG7 vcc_avdd**regulator-state-mem+LDO_REG8 vccio_sdw@2Z regulator-state-mem+LDO_REG9 vcc3v3_sd2Z2Zregulator-state-mem+SWITCH_REG1vcc_5v0SWITCH_REG2vcc_3v35i2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c@  " i2cpclkdefault disabledserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uartA n6  baudclkapb_pclkx}txrxdefault  disabledpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwmC  pwmpclk#default! disabledclock-controller@ff480000rockchip,rv1126-pmucruH"clock-controller@ff490000rockchip,rv1126-cruI#xin24m"dma-controller@ff4e0000arm,pl330arm,primecellN@ apb_pclkpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwmU0 pwmpclk'$defaultokayserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uartV n6baudclkapb_pclkx}txrxdefault %&'okaybluetoothqcom,qca9377-bt( )default*  serial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uartW n6baudclkapb_pclkx }txrxdefault+okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uartX n6baudclkapb_pclkx  }txrxdefault, disabledserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uartY n6baudclkapb_pclkx  }txrxdefault- disabledserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uartZ n6 baudclkapb_pclkx}txrxdefault. disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc^ ( , saradcapb_pclk; "saradc-apbokay. timer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timerf   - pclktimervop@ffb00000rockchip,rv1126-vop  ;aclk_vopdclk_vophclk_vop "axiahbdclk:/A0  disabledportendpoint@0endpoint@1iommu@ffb00f00rockchip,iommu ; aclkifaceOA0  disabled/ethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a@_`\macirqeth_wake_irq"@~Tstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_ref "stmmacethl}123okay~} sY@}x@input4rgmii5default6789$*-mdiosnps,dwmac-mdioethernet-phy@0ethernet-phy-id001c.c916default:6N F X4stmmac-axi-configdt1rx-queues-config2queue0tx-queues-config3queue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ N rstbiuciuciu-driveciu-sample A0okaydefault ;<=Z 5 mmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ L lmnbiuciuciu-driveciu-sample okay"4Edefault>?@AZWdq mmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ M opqbiuciuciu-driveciu-sampleA0okay4Bdefault CDEZq  spi@ffc90000 rockchip,sfc@ PvĴclk_sfchclk_sfcvA0okaydefaultFflash@0jedec,spi-norpinctrlrockchip,rv1126-pinctrl"gpio@ff460000rockchip,gpio-bankF "&gpio@ff620000rockchip,gpio-bankb #(Ogpio@ff630000rockchip,gpio-bankc $)gpio@ff640000rockchip,gpio-bankd %*)gpio@ff650000rockchip,gpio-banke & +pcfg-pull-upJpcfg-pull-downIpcfg-pull-none-Gpcfg-pull-none-drv-level-3-:Lpcfg-pull-up-drv-level-2:Hpcfg-pull-none-drv-level-0-smt-:IKclk_out_ethernetclk-out-ethernetm1-pins^G9emmcemmc-bus8^HHHHHHHH;emmc-clk^H=emmc-cmd^H<fspifspi-pins`^IJJJJJFi2c0i2c0-xfer ^ K Ki2c2i2c2-xfer ^KKpwm2pwm2m0-pins^G!pwm11pwm11m0-pins^G$rgmiirgmiim1-miim ^GG6rgmiim1-bus2`^ GG GLLL7rgmiim1-bus4`^GGGLLL8sdmmc0sdmmc0-bus4@^HHHH@sdmmc0-clk^H>sdmmc0-cmd^ H?sdmmc0-det^GAsdmmc1sdmmc1-bus4@^ H HHHEsdmmc1-clk^ HCsdmmc1-cmd^ HDuart0uart0-xfer ^JJ%uart0-ctsn^G&uart0-rtsn^G'uart1uart1m0-xfer ^JJ uart2uart2m1-xfer ^JJ+uart3uart3m0-xfer ^JJ,uart4uart4m0-xfer ^JJ-uart5uart5m0-xfer ^JJ.btbt-enable^G*flashflash-vol-sel^ GMpmicpmic-int-l^ Jwifiwifi-enable-h^GNetherneteth-phy-rst^I:vccio-flash-regulatorregulator-fixedl  defaultM vccio_flashw@w@5 pwrseq-sdiommc-pwrseq-simple( ext_clockdefaultN XOBchosenserial2:1500000n8vcc12v-dcin-regulatorregulator-fixed vcc12v_dcinPvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@Pv3v3-sys-regulatorregulator-fixed v3v3_sys2Z2Z #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2serial0serial1serial2serial3serial4serial5mmc0device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltdmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstenable-gpiosmax-speedvddxo-supplyvddio-supply#io-channel-cellsresetsreset-namesvref-supplyiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configassigned-clocksassigned-clock-parentsassigned-clock-ratesclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthnon-removablerockchip,default-sample-phasevmmc-supplyvqmmc-supplycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr104cap-sdio-irqkeep-power-in-suspendmmc-pwrseqspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsenable-active-highgpiovin-supplystdout-path