q8jp(j8#geniatech,xpi-3128rockchip,rk3128 +7Geniatech XPI-3128aliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/ethernet@2008c000/mmc@1021c000/mmc@10214000arm-pmuarm,cortex-a7-pmu0LMNOcpus+rockchip,rk3036-smpcpu@f00cpuarm,cortex-a7@cpu@f01cpuarm,cortex-a7cpu@f02cpuarm,cortex-a7cpu@f03cpuarm,cortex-a7opp-table-0operating-points-v2#opp-216000000.  5~~7opp-408000000.Q 5~~7opp-600000000.#F 5~~7opp-696000000.)| 57opp-816000000.0, 5g8g87Copp-1008000000.< 5OO7opp-1200000000.G 5777display-subsystemrockchip,display-subsystemO Uokayopp-table-1operating-points-v2 opp-200000000.  5opp-300000000. 5opp-400000000.ׄ 500opp-480000000.8 5timerarm,armv7-timer0   \n6oscillator fixed-clockn6xin24m0sram@10080000 mmio-sram +  smp-sram@0rockchip,rk3066-smp-sramgpu@10090000"rockchip,rk3128-maliarm,mali-400 Hgpgpmmupp0ppmmu0pp1ppmmu1 buscore x Uokay syscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd power-controller!rockchip,rk3128-power-controller+ power-domain@1Erz power-domain@2(power-domain@3vop@1010e000rockchip,rk3126-vop aclk_vopdclk_vophclk_vopdef axiahbdclk Uokayport+ endpoint@05endpoint@1dsi@10110000*rockchip,rk3128-mipi-dsisnps,dw-mipi-dsi@ !Epclk$)dphy apb3 Udisabledports+port@0endpointport@1qos@1012d000rockchip,rk3128-qossyscon qos@1012e000rockchip,rk3128-qossyscon qos@1012f000rockchip,rk3128-qossyscon qos@1012f080rockchip,rk3128-qossyscon  qos@1012f100rockchip,rk3128-qossyscon qos@1012f180rockchip,rk3128-qossyscon qos@1012f200rockchip,rk3128-qossyscon interrupt-controller@10139000arm,cortex-a7-gic     @Uusb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2 otgfotgn@ $ )usb2-phyUokayusb@101c0000 generic-ehci $)usbUokayusb@101e0000 generic-ohci $)usb Udisabledi2s@10200000(rockchip,rk3128-i2srockchip,rk3066-i2s  DPi2s_clki2s_hclktxrx Udisabledspdif@10204000,rockchip,rk3128-spdifrockchip,rk3066-spdif @ 7S mclkhclk txdefault Udisabledspi@1020c000 rockchip,sfc  2clk_sfchclk_sfc Udisabledmmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@@  Drvbiuciuciu-driveciu-sample rx-txрQresetUokay default !"#!,=Dmmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Eswbiuciuciu-driveciu-sample rx-txрRreset Udisabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Guybiuciuciu-driveciu-sample rx-txрSresetUokay default $%&L^kDi2s@10220000(rockchip,rk3128-i2srockchip,rk3066-i2s" Qi2s_clki2s_hclktxrxqdefault' Udisablednand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfcP@ Cahbnfcdefault ()*+,-./ Udisabledclock-controller@20000000rockchip,rk3128-cru 0xin24m3#gsyscon@20008000&rockchip,rk3128-grfsysconsimple-mfd +usb2phy@17crockchip,rk3128-usb2phy| phyclk usb480m_phy1Uokay1host-port 5 linestateUokayotg-port$#34otg-bvalidotg-idlinestateUokayhdmi@20034000rockchip,rk3128-inno-hdmi @@ -G pclkrefdefault 234 Uokayports+port@0endpoint5port@1endpoint6Qphy@20038000rockchip,rk3128-dsi-dphy @r refpclk $apb Udisabledtimer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer @  aU pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer @  aV pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer @@  ;aW pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer @`  <aX pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer @  =aY pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer @  >aZ pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt  "? Udisabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default7 Udisabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default8Uokay]pwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm  ^default9Uokay^pwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm 0^default: Udisabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c ` i2cMdefault;+ Udisabledi2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cNdefault<+ Udisabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cOdefault=+ Udisabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart  n6MUbaudclkapb_pclktxrxdefault >?@ Udisabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart @ n6NVbaudclkapb_pclktxrxdefaultAUokayserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart  n6OWbaudclkapb_pclktxrxdefaultB Udisabledsaradc@2006c000rockchip,saradc  [>saradcapb_pclkW saradc-apbUokayPi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c   i2cLdefaultC+ Udisabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi @ ARspiclkapb_pclk txrxdefaultDEFGH+ Udisableddma-controller@20078000arm,pl330arm,primecell @ ; apb_pclkRethernet@2008c000rockchip,rk3128-gmac @89macirqeth_wake_irq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 stmmaceth3]kUokayyoutputIrmiiJ|defaultKmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22d  LdefaultMJpinctrlrockchip,rk3128-pinctrl3+gpio@2007c000rockchip,gpio-bank  $@@UHEADER_5HEADER_3HEADER_22HEADER_23HEADER_19HEADER_26HEADER_21HEADER_24HEADER_18HEADER_36HEADER_13Vgpio@20080000rockchip,gpio-bank  %A@UpHEADER_7HEADER_35HEADER_33HEADER_37HEADER_40HEADER_38HEADER_11HEADER_29HEADER_31Zgpio@20084000rockchip,gpio-bank @ &B@U:HEADER_27HEADER_8HEADER_10Lgpio@20088000rockchip,gpio-bank  'C@U;HEADER_32HEADER_12HEADER_15Rpcfg-pull-default Opcfg-pull-noneNemmcemmc-clk,N$emmc-cmd,O%emmc-cmd1,Oemmc-pwr,Oemmc-bus1,Oemmc-bus4@,OOOOemmc-bus8,OOOOOOOO&gmacrgmii-pins,O O O O OOOOOOOOOOOrmii-pins,O O OOOOOOOOKhdmihdmii2c-xfer ,NN2hdmi-hpd,N3hdmi-cec,N4i2c0i2c0-xfer ,NNCi2c1i2c1-xfer ,NN;i2c2i2c2-xfer ,NN<i2c3i2c3-xfer ,NN=i2si2s-bus`,N N N N NN'i2s1-bus`,NNNNNNlcdclcdc-dclk,Nlcdc-den, Nlcdc-hsync, Nlcdc-vsync, Nlcdc-rgb24, N NNNNNNNNNNNNNnfcflash-ale,N(flash-cle,N*flash-wrn,N/flash-rdn,N-flash-rdy,N.flash-cs0,N+flash-dqs,N,flash-bus8,NNNNNNNN)pwm0pwm0-pin,N7pwm1pwm1-pin,N8pwm2pwm2-pin,N9pwm3pwm3-pin,N:sdiosdio-clk,Nsdio-cmd,Osdio-pwren,Osdio-bus4@,OOOOsdmmcsdmmc-clk,N!sdmmc-cmd,O"sdmmc-det,O#sdmmc-wp,Osdmmc-pwren,O[sdmmc-bus4@,OOOO sfcsfc-bus2 ,OOsfc-bus4@,OOOOsfc-clk,Nsfc-cs0,Osfc-cs1,Ospdifspdif-tx,Nspi0spi0-clk,OFspi0-cs0, OGspi0-tx, ODspi0-rx, OEspi0-cs1, OHspi1-clk,Ospi1-cs0,Ospi1-tx,Ospi1-rx,Ospi1-cs1,Ospi2-clk, Ospi2-cs0,Ospi2-tx, Ospi2-rx, Ouart0uart0-xfer ,ON>uart0-cts,N?uart0-rts,N@uart1uart1-xfer , O OAuart1-cts,Nuart1-rts, Nuart2uart2-xfer ,ONBuart2-cts,Nuart2-rts,Ndp83848cdp83848c-rst,NMir-receiverir-int,NUledspower-led,NWspd-led, NXusb2host-drv,NTmemory@60000000memory`@chosen:/serial@20064000adc-keys adc-keysFPRbuttonsc2Zbutton-recovery }Recoveryhdc-5v-regulatorregulator-fixedDC_5VLK@LK@Shdmi-connnectorhdmi-connectoraportendpointQ6host-pwr-5v-regulatorregulator-fixed  R HOST_PWR_5VLK@LK@#SdefaultT.ir-receivergpio-ir-receiver RdefaultUleds gpio-ledsled-power VApowerJPondefaultWled-spd R AlanJdefaultXmcu3v3-regulatorregulator-fixedMCU3V32Z2Z#vcc-ddr-regulatorregulator-fixedVCC_DDR``#Yvcc-io-regulatorregulator-fixedVCC_IO2Z2Z#Yvcc-lan-regulatorregulator-fixedVCC_LAN2Z2Z#Ivcc-sd-regulatorregulator-fixed  ZVCC_SD2Z2Z#default[vcc-sys-regulatorregulator-fixedVCC_SYSLK@LK@#SYvcc33-hdmi-regulatorregulator-fixed VCC33_HDMI2Z2Z#\vcca-33-regulatorregulator-fixedVCCA_332Z2Z#Y\vdd-11-regulatorregulator-fixedVDD_11#Yvdd11-hdmi-regulatorregulator-fixed VDD11_HDMI#vdd-arm-regulatorpwm-regulatorVDD_ARM^]acY \vdd-log-regulatorpwm-regulatorVDD_LOG^^andcY\  compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2ethernet0mmc0mmc1interruptsinterrupt-affinityenable-methoddevice_typeregclock-latencyclocksresetsoperating-points-v2#cooling-cellscpu-supplyphandleopp-sharedopp-hzopp-microvoltopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domainsmali-supply#power-domain-cellspm_qosreset-namesremote-endpointphysphy-namesrockchip,grfinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevusb_a-supplyvusb_d-supplydmasdma-names#sound-dai-cellspinctrl-namespinctrl-0fifo-depthmax-frequencybus-widthvmmc-supplydisable-wpcap-sd-highspeedno-mmcno-sdiocap-mmc-highspeedmmc-ddr-3_3vno-sdrockchip,playback-channels#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsvref-supplyarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthclock_in_outphy-supplyphy-modephy-handlemax-speedreset-assert-usreset-deassert-usreset-gpiosgpio-controller#gpio-cellsgpio-line-namesbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-ongpiostartup-delay-usvin-supplyenable-active-highfunctioncolordefault-statepwmspwm-supplypwm-dutycycle-rangeregulator-ramp-delay