^8Z@(Z$rockchip,rk3128-evbrockchip,rk3128 +!7Rockchip RK3128 Evaluation boardaliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/mmc@1021c000arm-pmuarm,cortex-a7-pmu0LMNOcpus+rockchip,rk3036-smpcpu@f00cpuarm,cortex-a7@cpu@f01cpuarm,cortex-a7cpu@f02cpuarm,cortex-a7cpu@f03cpuarm,cortex-a7opp-table-0operating-points-v2 opp-216000000  ~~7opp-408000000Q ~~7opp-600000000#F ~~7opp-696000000)| 7opp-8160000000, g8g87)opp-1008000000< OO7opp-1200000000G 777display-subsystemrockchip,display-subsystem5 ;disabledopp-table-1operating-points-v2 opp-200000000  opp-300000000 opp-400000000ׄ 00opp-4800000008 timerarm,armv7-timer0   Bfn6oscillator fixed-clockfn6vxin24m(sram@10080000 mmio-sram +  smp-sram@0rockchip,rk3066-smp-sramgpu@10090000"rockchip,rk3128-maliarm,mali-400 Hgpgpmmupp0ppmmu0pp1ppmmu1 buscore x  ;disabledsyscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd power-controller!rockchip,rk3128-power-controller+ power-domain@1Erz power-domain@2(power-domain@3vop@1010e000rockchip,rk3126-vop aclk_vopdclk_vophclk_vopdef axiahbdclk  ;disabledport+endpoint@0-endpoint@1dsi@10110000*rockchip,rk3128-mipi-dsisnps,dw-mipi-dsi@ !Epclkdphy apb  ;disabledports+port@0endpointport@1qos@1012d000rockchip,rk3128-qossyscon qos@1012e000rockchip,rk3128-qossyscon qos@1012f000rockchip,rk3128-qossyscon qos@1012f080rockchip,rk3128-qossyscon  qos@1012f100rockchip,rk3128-qossyscon  qos@1012f180rockchip,rk3128-qossyscon  qos@1012f200rockchip,rk3128-qossyscon interrupt-controller@10139000arm,cortex-a7-gic     /usb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2 otg@otgHZi@  usb2-phy;okayxusb@101c0000 generic-ehci usb;okayusb@101e0000 generic-ohci usb;okayi2s@10200000(rockchip,rk3128-i2srockchip,rk3066-i2s  DPi2s_clki2s_hclktxrx ;disabledspdif@10204000,rockchip,rk3128-spdifrockchip,rk3066-spdif @ 7S mclkhclk txdefault ;disabledspi@1020c000 rockchip,sfc  2clk_sfchclk_sfc ;disabledmmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@@  Drvbiuciuciu-driveciu-sample rx-txрQreset ;disabledmmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Eswbiuciuciu-driveciu-sample rx-txрRreset ;disabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Guybiuciuciu-driveciu-sample rx-txрSreset;okaydefault i2s@10220000(rockchip,rk3128-i2srockchip,rk3066-i2s" Qi2s_clki2s_hclktxrxdefault ;disablednand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfcP@ Cahbnfcdefault  !"#$%&' ;disabledclock-controller@20000000rockchip,rk3128-cru (xin24m #gsyscon@20008000&rockchip,rk3128-grfsysconsimple-mfd +usb2phy@17crockchip,rk3128-usb2phy| phyclk vusb480m_phy,);okay)host-port 5 linestateC;okayotg-port$#34otg-bvalidotg-idlinestateC;okayhdmi@20034000rockchip,rk3128-inno-hdmi @@ -G pclkrefdefault *+,  ;disabledports+port@0endpoint-port@1phy@20038000rockchip,rk3128-dsi-dphy @r refpclkC $apb ;disabledtimer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer @  aU pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer @  aV pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer @@  ;aW pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer @`  <aX pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer @  =aY pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer @  >aZ pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt  "? ;disabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default.N ;disabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default/N ;disabledpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm  ^default0N ;disabledpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm 0^default1N ;disabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c ` i2cMdefault2+;okayrtc@51haoyu,hym8563Qvxin32ki2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cNdefault3+ ;disabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cOdefault4+ ;disabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart  fn6MUbaudclkapb_pclktxrxdefault 567Yf ;disabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart @ fn6NVbaudclkapb_pclktxrxdefault8Yf ;disabledserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart  fn6OWbaudclkapb_pclktxrxdefault9Yf ;disabledsaradc@2006c000rockchip,saradc  [>saradcapb_pclkW saradc-apbp ;disabledi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c   i2cLdefault:+ ;disabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi @ ARspiclkapb_pclk txrxdefault;<=>?+ ;disableddma-controller@20078000arm,pl330arm,primecell @ apb_pclkethernet@2008c000rockchip,rk3128-gmac @89macirqeth_wake_irq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 stmmaceth  ;disabledmdiosnps,dwmac-mdio+pinctrlrockchip,rk3128-pinctrl +gpio@2007c000rockchip,gpio-bank  $@/Bgpio@20080000rockchip,gpio-bank  %A/gpio@20084000rockchip,gpio-bank @ &B/Dgpio@20088000rockchip,gpio-bank  'C/pcfg-pull-defaultApcfg-pull-none @emmcemmc-clk@emmc-cmdAemmc-cmd1Aemmc-pwrAemmc-bus1Aemmc-bus4@AAAAemmc-bus8AAAAAAAAgmacrgmii-pinsA A A A AAAAAAAAAAArmii-pinsA A AAAAAAAAhdmihdmii2c-xfer @@*hdmi-hpd@+hdmi-cec@,i2c0i2c0-xfer @@:i2c1i2c1-xfer @@2i2c2i2c2-xfer @@3i2c3i2c3-xfer @@4i2si2s-bus`@ @ @ @ @@i2s1-bus`@@@@@@lcdclcdc-dclk@lcdc-den @lcdc-hsync @lcdc-vsync @lcdc-rgb24 @ @@@@@@@@@@@@@nfcflash-ale@ flash-cle@"flash-wrn@'flash-rdn@%flash-rdy@&flash-cs0@#flash-dqs@$flash-bus8@@@@@@@@!pwm0pwm0-pin@.pwm1pwm1-pin@/pwm2pwm2-pin@0pwm3pwm3-pin@1sdiosdio-clk@sdio-cmdAsdio-pwrenAsdio-bus4@AAAAsdmmcsdmmc-clk@sdmmc-cmdAsdmmc-detAsdmmc-wpAsdmmc-pwrenAsdmmc-bus4@AAAAsfcsfc-bus2 AAsfc-bus4@AAAAsfc-clk@sfc-cs0Asfc-cs1Aspdifspdif-tx@spi0spi0-clkA=spi0-cs0 A>spi0-tx A;spi0-rx A<spi0-cs1 A?spi1-clkAspi1-cs0Aspi1-txAspi1-rxAspi1-cs1Aspi2-clk Aspi2-cs0Aspi2-tx Aspi2-rx Auart0uart0-xfer A@5uart0-cts@6uart0-rts@7uart1uart1-xfer  A A8uart1-cts@uart1-rts @uart2uart2-xfer A@9uart2-cts@uart2-rts@usb-hosthost-vbus-drv@Eusb-otgotg-vbus-drv@Cchosen(/serial@20068000memory@60000000memory`@vcc5v0-otg-regulatorregulator-fixed 4BdefaultC 9vcc5v0_otgHLK@`LK@vcc5v0-host-regulatorregulator-fixed 4DdefaultE 9vcc5v0_hostxHLK@`LK@ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2mmc0interruptsinterrupt-affinityenable-methoddevice_typeregclock-latencyclocksresetsoperating-points-v2#cooling-cellsphandleopp-sharedopp-hzopp-microvoltopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domains#power-domain-cellspm_qosreset-namesremote-endpointphysphy-namesrockchip,grfinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevbus-supplydmasdma-names#sound-dai-cellspinctrl-namespinctrl-0fifo-depthmax-frequencybus-widthrockchip,playback-channels#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathgpioregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-on