D8(H ,qnap,ts433rockchip,rk3568 7Qnap TS-433-4G NAS System 4-Bayaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000cpus cpu@0cpu,arm,cortex-a55psci%2@DQ^@p} cpu@100cpu,arm,cortex-a55psci%2@DQ^@p} cpu@200cpu,arm,cortex-a55psci%2@DQ^@p} cpu@300cpu,arm,cortex-a55psci%2@DQ^@p} l3-cache,cache'4@Fopp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0opp-1992000000v 000display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc protocol@14opp-table-1,operating-points-v2<opp-200000000   P PB@opp-300000000  P PB@opp-400000000ׄ  P PB@opp-600000000#F  B@opp-700000000)' ~~B@opp-800000000/ B@B@B@hdmi-sound,simple-audio-cardHDMI(i2sA [disabledsimple-audio-card,codecbsimple-audio-card,cpubpmu,arm,cortex-a55-pmu0lw psci ,arm,psci-1.0 smctimer,arm,armv8-timer0l   xin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32k defaultsram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob l_ sata-phy [disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob l` sata-phy [disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ lref_clksuspend_clkbus_clkotg &utmi_wide/6 [disabled usb2-phyusb3-phyusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ lref_clksuspend_clkbus_clkhost usb2-phyusb3-phy &utmi_wide/6 [disabledinterrupt-controller@fd400000 ,arm,gic-v3 @F l OduA(usb@fd800000 ,generic-ehci lusb [disabledusb@fd840000 ,generic-ohci lusb [disabledusb@fd880000 ,generic-ehci lusb [disabledusb@fd8c0000 ,generic-ohci lusb [disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdHio-domains&,rockchip,rk3568-pmu-io-voltage-domain [disabledsyscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucruclock-controller@fdd20000,rockchip,rk3568-cruxin24m G i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c l.- i2cpclkdefault  [disabledpmic@20,rockchip,rk809 lserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart lt ,baudclkapb_pclkdefault [disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclkdefault  [disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclkdefault  [disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk default  [disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk!default  [disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller power-domain@7*"power-domain@8 *#$%power-domain@9  *&'(power-domain@10 *)*+,-.power-domain@11 */power-domain@13 *0power-domain@14 *123power-domain@15 *456789:;gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$l()' 1jobmmugpugpubus< [disabledvideo-codec@fdea0400,rockchip,rk3568-vpu l1vdpu aclkhclkA= iommu@fdea0800,rockchip,rk3568-iommu@ l aclkiface H=rga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga lZaclkhclksclk/&$% Ucoreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu l@ aclkhclkA> iommu@fdee0800,rockchip,rk3568-iommu@ l? aclkiface H>mmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ ld biuciuciu-driveciu-samplealр/Ureset [disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20al 1macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref/ Ustmmacethz?@A [disabledmdio,snps,dwmac-mdio stmmac-axi-config?rx-queues-config@queue0tx-queues-config Aqueue0vop@fe040000 0@ vopgamma-lut l(%aclkhclkdclk_vp0dclk_vp1dclk_vp2AB  [disabled,rockchip,rk3568-vopports port@0 port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? l aclkifaceH  [disabledBdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi lDpclkdphyC Uapb/ [disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi lEpclkdphyD Uapb/ [disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  l-((iahbisfrcecrefdefault EFG * [disabledports port@0port@1qos@fe128000,rockchip,rk3568-qossyscon "qos@fe138080,rockchip,rk3568-qossyscon 1qos@fe138100,rockchip,rk3568-qossyscon 2qos@fe138180,rockchip,rk3568-qossyscon 3qos@fe148000,rockchip,rk3568-qossyscon #qos@fe148080,rockchip,rk3568-qossyscon $qos@fe148100,rockchip,rk3568-qossyscon %qos@fe150000,rockchip,rk3568-qossyscon /qos@fe158000,rockchip,rk3568-qossyscon )qos@fe158100,rockchip,rk3568-qossyscon *qos@fe158180,rockchip,rk3568-qossyscon +qos@fe158200,rockchip,rk3568-qossyscon ,qos@fe158280,rockchip,rk3568-qossyscon -qos@fe158300,rockchip,rk3568-qossyscon .qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon 4qos@fe190280,rockchip,rk3568-qossyscon 8qos@fe190300,rockchip,rk3568-qossyscon 9qos@fe190380,rockchip,rk3568-qossyscon :qos@fe190400,rockchip,rk3568-qossyscon ;qos@fe198000,rockchip,rk3568-qossyscon 0qos@fe1a8000,rockchip,rk3568-qossyscon &qos@fe1a8080,rockchip,rk3568-qossyscon 'qos@fe1a8100,rockchip,rk3568-qossyscon (dfi@fe230000,rockchip,rk3568-dfi# l ;Hpcie@fe260000,rockchip,rk3568-pcie0@& dbiapbconfig<lKJIHG1syspmcmsglegacyerrH($aclk_mstaclk_slvaclk_dbipclkauxpcidR`eIIIIs pcie-phyT @@/Upipe  [disabledlegacy-interrupt-controllerdO lHImmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ lb biuciuciu-driveciu-samplealр/Ureset [disabledmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ lc biuciuciu-driveciu-samplealр/Ureset [disabledspi@fe300000 ,rockchip,sfc0@ lexvclk_sfchclk_sfcJdefault [disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 l{} n6(|zy{}corebusaxiblocktimer[okayl i2s@fe400000,rockchip,rk3568-i2s-tdm@ l4=AFqFq?C9mclk_txmclk_rxhclkKtx/PQ Utx-mrx-m* [disabledi2s@fe410000,rockchip,rk3568-i2s-tdmA l5EIFqFqGK:mclk_txmclk_rxhclkKKrxtx/RS Utx-mrx-mdefault0LMNOPQRSTUVW* [disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB l6MFqOO;mclk_txmclk_rxhclkKKtxrx/TUtx-mdefaultXYZ[* [disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC l7SW<mclk_txmclk_rxhclkKKtxrx/UV Utx-mrx-m* [disabledpdm@fe440000,rockchip,rk3568-pdmD lLZYpdm_clkpdm_hclkK rx\]^_`adefault/XUpdm-m* [disabledspdif@fe460000,rockchip,rk3568-spdifF lf mclkhclk_\Ktxdefaultb* [disableddma-controller@fe530000,arm,pl330arm,primecellS@l   apb_pclkdma-controller@fe550000,arm,pl330arm,primecellU@l  apb_pclkKi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ l/HG i2cpclkcdefault [okayrtc@51,microcrystal,rv8263Qi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ l0JI i2cpclkddefault  [disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ l1LK i2cpclkedefault  [disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] l2NM i2cpclkfdefault  [disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ l3PO i2cpclkgdefault  [disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` l tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia lgRQspiclkapb_pclktxrxdefault hij  [disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib lhTSspiclkapb_pclktxrxdefault klm  [disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic liVUspiclkapb_pclktxrxdefault nop  [disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid ljXWspiclkapb_pclktxrxdefault qrs  [disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte lubaudclkapb_pclktdefault [disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf lv# baudclkapb_pclkudefault[okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg lw'$baudclkapb_pclkvdefault [disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth lx+(baudclkapb_pclk wdefault [disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti ly/,baudclkapb_pclk  xdefault [disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj lz30baudclkapb_pclk  ydefault [disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk l{74baudclkapb_pclkzdefault [disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl l|;8baudclkapb_pclk{default [disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm l}?<baudclkapb_pclk|default [disabledthermal-zonescpu-thermald+9}tripscpu_alert0IpUpassive~cpu_alert1I$Upassivecpu_critIsU criticalcooling-mapsmap0`~0e gpu-thermal+9}tripsgpu-thresholdIpUpassivegpu-targetI$Upassivegpu-critIsU criticalcooling-mapsmap0` etsadc@fe710000,rockchip,rk3568-tsadcq lsf@ `tsadcapb_pclk/tsdefaultsleep [disabled}saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr l]saradcapb_pclk/ Usaradc-apb [disabledpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault  [disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault  [disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault  [disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault  [disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault  [disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault  [disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault  [disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault  [disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault  [disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault  [disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault  [disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault  [disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe"/ [disabledphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe%/ [disabledphy@fe870000,rockchip,rk3568-csi-dphyypclk/Uapb [disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz Uapb/ [disabledCmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ Uapb/ [disabledDusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m l [disabledhost-port [disabledotg-port [disabledusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m l [disabledhost-port [disabledotg-port [disabledpinctrl,rockchip,rk3568-pinctrl;H gpio@fdd60000,rockchip,gpio-bank l!.  Odgpio@fe740000,rockchip,gpio-bankt l"cd Odgpio@fe750000,rockchip,gpio-banku l#ef@ Odgpio@fe760000,rockchip,gpio-bankv l$gh` Odgpio@fe770000,rockchip,gpio-bankw l%ij Odpcfg-pull-up(pcfg-pull-none5pcfg-pull-none-drv-level-15Bpcfg-pull-none-drv-level-25Bpcfg-pull-none-drv-level-35Bpcfg-pull-up-drv-level-1(Bpcfg-pull-up-drv-level-2(Bpcfg-pull-none-smt5Qacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0f cpuebcedpdpemmceth0eth1flashfspifspi-pins`fJgmac0gmac0-miim fgmac0-rx-bus20fgmac0-tx-bus20f   gmac0-rgmii-clk fgmac0-rgmii-bus@fgmac1gpuhdmitxhdmitxm0-cecfGhdmitx-sclfEhdmitx-sdafFi2c0i2c0-xfer f  i2c1i2c1-xfer f  ci2c2i2c2m0-xfer f di2c3i2c3m0-xfer fei2c4i2c4m0-xfer f  fi2c5i2c5m0-xfer f  gi2s1i2s1m0-lrckrxfOi2s1m0-lrcktxfNi2s1m0-sclkrxfMi2s1m0-sclktxfLi2s1m0-sdi0f Pi2s1m0-sdi1f Qi2s1m0-sdi2f Ri2s1m0-sdi3fSi2s1m0-sdo0fTi2s1m0-sdo1fUi2s1m0-sdo2f Vi2s1m0-sdo3f Wi2s2i2s2m0-lrcktxfYi2s2m0-sclktxfXi2s2m0-sdifZi2s2m0-sdof[i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clkf\pdmm0-clk1f]pdmm0-sdi0f ^pdmm0-sdi1f _pdmm0-sdi2f `pdmm0-sdi3fapmicpmupwm0pwm0m0-pinsfpwm1pwm1m0-pinsfpwm2pwm2m0-pinsf pwm3pwm3-pinsf!pwm4pwm4-pinsfpwm5pwm5-pinsfpwm6pwm6-pinsfpwm7pwm7-pinsfpwm8pwm8m0-pinsf pwm9pwm9m0-pinsf pwm10pwm10m0-pinsf pwm11pwm11m0-pinsfpwm12pwm12m0-pinsfpwm13pwm13m0-pinsfpwm14pwm14m0-pinsfpwm15pwm15m0-pinsfrefclksatasata0sata1sata2scrsdmmc0sdmmc1sdmmc2spdifspdifm0-txfbspi0spi0m0-pins0f jspi0m0-cs0fhspi0m0-cs1fispi1spi1m0-pins0f mspi1m0-cs0fkspi1m0-cs1flspi2spi2m0-pins0fpspi2m0-cs0fnspi2m0-cs1fospi3spi3m0-pins0f  sspi3m0-cs0fqspi3m0-cs1frtsadctsadc-shutorgftsadc-pinfuart0uart0-xfer fuart1uart1m0-xfer f  tuart2uart2m0-xfer fuuart3uart3m0-xfer fvuart4uart4m0-xfer fwuart5uart5m0-xfer fxuart6uart6m0-xfer fyuart7uart7m0-xfer fzuart8uart8m0-xfer f{uart9uart9m0-xfer f|vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob l^ sata-phy [disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon 5qos@fe190100,rockchip,rk3568-qossyscon 6qos@fe190200,rockchip,rk3568-qossyscon 7syscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy&'wrefclk_mrefclk_npclk/Uphyt[okaypcie@fe270000,rockchip,rk3568-pcie H($aclk_mstaclk_slvaclk_dbipclkauxpci<l1syspmcmsglegacyerrdR`es pcie-phy0@@'T @@@ dbiapbconfig/Upipe[okay legacy-interrupt-controllerOd lpcie@fe280000,rockchip,rk3568-pcie H($aclk_mstaclk_slvaclk_dbipclkauxpci<l1syspmcmsglegacyerrdR`es  pcie-phy0@(T @@ dbiapbconfig/Upipe [disabledlegacy-interrupt-controllerOd lethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*l1macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref/ Ustmmacethz[okaysY@outputrgmiidefault/<mdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22stmmac-axi-configrx-queues-configqueue0tx-queues-config queue0phy@fe820000,rockchip,rk3568-naneng-combphy| refapbpipe/ [disabled interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachephandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controller#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthnon-removabledma-namesarm,pl330-periph-burst#dma-cellswakeup-sourcepolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cells#io-channel-cellsrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfreset-gpiosclock_in_outphy-handlephy-moderx_delaytx_delay