i8t( < ,radxa,zero-3erockchip,rk35667Radxa ZERO 3Ealiases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe2b0000cpus cpu@0cpu,arm,cortex-a55psci 4A@S`m@ cpu@100cpu,arm,cortex-a55psci 4A@S`m@ cpu@200cpu,arm,cortex-a55psci 4A@S`m@ cpu@300cpu,arm,cortex-a55psci 4A@S`m@ l3-cache,cache6C@Uopp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc  protocol@14opp-table-1,operating-points-v2Copp-200000000   P PB@opp-300000000  P PB@opp-400000000ׄ  P PB@opp-600000000#F  B@opp-700000000)' ~~B@opp-800000000/ B@B@B@hdmi-sound,simple-audio-card+HDMIBi2s[uokaysimple-audio-card,codec|simple-audio-card,cpu| pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob _  sata-phy* udisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob `  sata-phy* udisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clk 8peripheral @utmi_wide*IPuokay  usb2-phyi phigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clk8host  usb2-phyusb3-phy @utmi_wide*IPuokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  ~A(usb@fd800000 ,generic-ehci  usb udisabledusb@fd840000 ,generic-ohci  usb udisabledusb@fd880000 ,generic-ehci  usb udisabledusb@fd8c0000 ,generic-ohci  usb udisabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd^io-domains&,rockchip,rk3568-pmu-io-voltage-domainuokay*8syscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucruFclock-controller@fdd20000,rockchip,rk3568-cruxin24mFS cG x i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- i2cpclk!default uokaypmic@20,rockchip,rk817 rk817-clkout1rk817-clkout2"default#$$$$$$ $$"%regulatorsDCDC_REG1 .vdd_logic=Qcz pqregulator-state-mem DCDC_REG2 .vdd_gpu_npu=Qcz pqDregulator-state-memDCDC_REG3.vcc_ddr=Qcregulator-state-memDCDC_REG4 .vcc3v3_sys=Qcz2Z2Zdregulator-state-mem2ZLDO_REG1 .vcca1v8_pmu=Qzw@w@regulator-state-memw@LDO_REG2 .vdda_0v9=Qz  Zregulator-state-memLDO_REG3 .vdda0v9_pmu=Qz  regulator-state-mem LDO_REG4 .vccio_acodec=Qz2Z2Zregulator-state-memLDO_REG5 .vccio_sd=Qzw@2Zregulator-state-memLDO_REG6 .vcc3v3_pmu=Qz2Z2Zregulator-state-mem2ZLDO_REG7 .vcc_1v8_p=Qzw@w@regulator-state-memLDO_REG8 .vcc1v8_dvp=Qzw@w@regulator-state-memLDO_REG9 .vcc2v8_dvp=Qz**regulator-state-memBOOST .vcc5v_midu=QzLK@LK@%regulator-state-memOTG_SWITCH.vbusregulator-state-memregulator@40,rockchip,rk8600@ .vdd_cpu=Qz 45)$regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,baudclkapb_pclk4&&'default9F udisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(defaultP udisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)defaultP udisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk*defaultP udisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk+defaultP udisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller[ power-domain@7o,[power-domain@8 o-./[power-domain@9  o012[power-domain@10 o345678[power-domain@11 o9[power-domain@13 o:[power-domain@14 o;<=[power-domain@15o>?@AB[gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' vjobmmugpugpubus C*uokayDvideo-codec@fdea0400,rockchip,rk3568-vpu vvdpu aclkhclkE* iommu@fdea0800,rockchip,rk3568-iommu@  aclkiface* Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ZaclkhclksclkI&$% coreaxiahb* video-codec@fdee0000,rockchip,rk3568-vepu @ aclkhclkF* iommu@fdee0800,rockchip,rk3568-iommu@ ? aclkiface* Fmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d biuciuciu-driveciu-sampleрIreset udisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a vmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refI stmmaceth GHIuokaySxinput(J 3rgmii-id<defaultKLMNOPmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22defaultQGN WP iRJstmmac-axi-configuGrx-queues-configHqueue0tx-queues-configIqueue0vop@fe040000 0@vopgamma-lut (%aclkhclkdclk_vp0dclk_vp1dclk_vp2S*  uokay,rockchip,rk3566-vopSxports port@0 endpoint@2T\port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?  aclkiface* uokaySdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi Dpclkdphy U* apbI  udisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi Epclkdphy V* apbI  udisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -((iahbisfrcecrefdefault WXY* 9 uokayZ[ports port@0endpoint\Tport@1endpoint]qos@fe128000,rockchip,rk3568-qossyscon ,qos@fe138080,rockchip,rk3568-qossyscon ;qos@fe138100,rockchip,rk3568-qossyscon <qos@fe138180,rockchip,rk3568-qossyscon =qos@fe148000,rockchip,rk3568-qossyscon -qos@fe148080,rockchip,rk3568-qossyscon .qos@fe148100,rockchip,rk3568-qossyscon /qos@fe150000,rockchip,rk3568-qossyscon 9qos@fe158000,rockchip,rk3568-qossyscon 3qos@fe158100,rockchip,rk3568-qossyscon 4qos@fe158180,rockchip,rk3568-qossyscon 5qos@fe158200,rockchip,rk3568-qossyscon 6qos@fe158280,rockchip,rk3568-qossyscon 7qos@fe158300,rockchip,rk3568-qossyscon 8qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon >qos@fe190280,rockchip,rk3568-qossyscon ?qos@fe190300,rockchip,rk3568-qossyscon @qos@fe190380,rockchip,rk3568-qossyscon Aqos@fe190400,rockchip,rk3568-qossyscon Bqos@fe198000,rockchip,rk3568-qossyscon :qos@fe1a8000,rockchip,rk3568-qossyscon 0qos@fe1a8080,rockchip,rk3568-qossyscon 1qos@fe1a8100,rockchip,rk3568-qossyscon 2dfi@fe230000,rockchip,rk3568-dfi#  ^pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<KJIHGvsyspmcmsglegacyerr#($aclk_mstaclk_slvaclk_dbipclkauxpci-`@____N_n}  pcie-phy*T @@Ipipe  udisabledlegacy-interrupt-controller~ H_mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b biuciuciu-driveciu-sampleрIresetuokaydefault`abcdmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c biuciuciu-driveciu-sampleрIreset udisabledspi@fe300000 ,rockchip,sfc0@ exvclk_sfchclk_sfcedefault udisabledmmc@fe310000,rockchip,rk3568-dwcmshc1 S{}c n6(|zy{}corebusaxiblocktimer udisabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ 4S=AcFqFq?C9mclk_txmclk_rxhclk4ftxIPQ tx-mrx-m uokay i2s@fe410000,rockchip,rk3568-i2s-tdmA 5SEIcFqFqGK:mclk_txmclk_rxhclk4ffrxtxIRS tx-mrx-m default0ghijklmnopqr udisabledi2s@fe420000,rockchip,rk3568-i2s-tdmB 6SMcFqOO;mclk_txmclk_rxhclk4fftxrxITtx-m defaultstuv udisabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7SW<mclk_txmclk_rxhclk4fftxrxIUV tx-mrx-m  udisabledpdm@fe440000,rockchip,rk3568-pdmD LZYpdm_clkpdm_hclk4f rxwxyz{|defaultIXpdm-m udisabledspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk_\4ftxdefault} udisableddma-controller@fe530000,arm,pl330arm,primecellS@   apb_pclk&dma-controller@fe550000,arm,pl330arm,primecellU@  apb_pclkfi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ /HG i2cpclk~default  udisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0JI i2cpclkdefault  udisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1LK i2cpclkdefault  udisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2NM i2cpclkdefault  udisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3PO i2cpclkdefault  udisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia gRQspiclkapb_pclk4&&txrxdefault   udisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib hTSspiclkapb_pclk4&&txrxdefault   udisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic iVUspiclkapb_pclk4&&txrxdefault   udisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid jXWspiclkapb_pclk4&&txrxdefault   udisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte ubaudclkapb_pclk4&&default9F udisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v# baudclkapb_pclk4&&default9Fuokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w'$baudclkapb_pclk4&&default9F udisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x+(baudclkapb_pclk4&& default9F udisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y/,baudclkapb_pclk4& & default9F udisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z30baudclkapb_pclk4& & default9F udisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk {74baudclkapb_pclk4&&default9F udisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl |;8baudclkapb_pclk4&&default9F udisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm }?<baudclkapb_pclk4&&default9F udisabledthermal-zonescpu-thermal d  -tripscpu_alert0 =p Ipassivecpu_alert1 =$ Ipassivecpu_crit =s I criticalcooling-mapsmap0 T0 Y gpu-thermal   -tripsgpu-threshold =p Ipassivegpu-target =$ Ipassivegpu-crit =s I criticalcooling-mapsmap0 T Ytsadc@fe710000,rockchip,rk3568-tsadcq sScf@ `tsadcapb_pclkI  hsdefaultsleep  uokay  saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]saradcapb_pclkI saradc-apb uokay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultP udisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultP udisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultP udisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultP udisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultP udisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultP udisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultP udisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultP udisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultP udisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultP udisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultP udisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultP udisabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipeS"cI   uokayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipeS%cI    udisabledphy@fe870000,rockchip,rk3568-csi-dphyypclk Iapb  udisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz * apbI udisabledUmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ * apbI udisabledVusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m  "uokayhost-port uokayotg-port uokayusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m  " udisabledhost-port  udisabledotg-port  udisabledpinctrl,rockchip,rk3568-pinctrl ^ gpio@fdd60000,rockchip,gpio-bank !.  2 B  N~B Zpin-10 [GPIO0_D0]pin-08 [GPIO0_D1]"gpio@fe740000,rockchip,gpio-bankt "cd 2 B  N~S Zpin-03 [GPIO1_A0]pin-05 [GPIO1_A1]pin-37 [GPIO1_A4]gpio@fe750000,rockchip,gpio-banku #ef 2 B@  N~ Zgpio@fe760000,rockchip,gpio-bankv $gh 2 B`  N~0 Zpin-11 [GPIO3_A1]pin-13 [GPIO3_A2]pin-12 [GPIO3_A3]pin-35 [GPIO3_A4]pin-40 [GPIO3_A5]pin-38 [GPIO3_A6]pin-36 [GPIO3_A7]pin-15 [GPIO3_B0]pin-16 [GPIO3_B1]pin-18 [GPIO3_B2]pin-29 [GPIO3_B3]pin-31 [GPIO3_B4]pin-22 [GPIO3_C1]pin-32 [GPIO3_C2]pin-33 [GPIO3_C3]pin-07 [GPIO3_C4]Rgpio@fe770000,rockchip,gpio-bankw %ij 2 B  N~ Zpin-27 [GPIO4_B2]pin-28 [GPIO4_B3]pin-23 [GPIO4_C2]pin-19 [GPIO4_C3]pin-21 [GPIO4_C5]pin-24 [GPIO4_C6]pcfg-pull-up jpcfg-pull-none wpcfg-pull-none-drv-level-1 w pcfg-pull-none-drv-level-2 w pcfg-pull-none-drv-level-3 w pcfg-pull-up-drv-level-1 j pcfg-pull-up-drv-level-2 j pcfg-pull-none-smt w acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmceth0eth1flashfspifspi-pins` egmac0gmac1gmac1m1-miim Kgmac1m1-clkinout Pgmac1m1-rx-bus20  Mgmac1m1-tx-bus20 Lgmac1m1-rgmii-clk Ngmac1m1-rgmii-bus@ Ogmac1-rstn Qgpuhdmitxhdmitxm0-cec Yhdmitx-scl Whdmitx-sda Xi2c0i2c0-xfer  !i2c1i2c1-xfer  ~i2c2i2c2m0-xfer i2c3i2c3m0-xfer i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrckrx ji2s1m0-lrcktx ii2s1m0-sclkrx hi2s1m0-sclktx gi2s1m0-sdi0  ki2s1m0-sdi1  li2s1m0-sdi2  mi2s1m0-sdi3 ni2s1m0-sdo0 oi2s1m0-sdo1 pi2s1m0-sdo2  qi2s1m0-sdo3  ri2s2i2s2m0-lrcktx ti2s2m0-sclktx si2s2m0-sdi ui2s2m0-sdo vi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk wpdmm0-clk1 xpdmm0-sdi0  ypdmm0-sdi1  zpdmm0-sdi2  {pdmm0-sdi3 |pmicpmic-int-l #pmupwm0pwm0m0-pins (pwm1pwm1m0-pins )pwm2pwm2m0-pins *pwm3pwm3-pins +pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ `sdmmc0-clk asdmmc0-cmd bsdmmc0-det csdmmc1sdmmc2spdifspdifm0-tx }spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer 'uart1uart1m0-xfer   uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsuser-led2 chosen serial2:1500000n8hdmi-con,hdmi-connectordportendpoint]leds ,gpio-ledsdefaultled-green  on heartbeat o" heartbeatregulator-1v8-vcc,regulator-fixed.vcc_1v8=Qzw@w@)regulator-1v8-vcca,regulator-fixed .vcca_1v8=Qzw@w@)regulator-1v8-vcca-image,regulator-fixed.vcca1v8_image=Qzw@w@)[regulator-3v3-vcc,regulator-fixed.vcc_3v3=Qz2Z2Z)dregulator-5v0-vcc-sys,regulator-fixed.vcc_sys=QzLK@LK@$ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplydma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsgpio-line-namesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathcolordefault-statefunctionlinux,default-trigger