ٽ8T( i ",pine64,quartz64-brockchip,rk35667Pine64 Quartz64 Model Baliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe2b0000/mmc@fe310000/mmc@fe2c0000cpus cpu@0cpu,arm,cortex-a55 psci*>K@]jw@ cpu@100cpu,arm,cortex-a55 psci*>K@]jw@ cpu@200cpu,arm,cortex-a55 psci*>K@]jw@ cpu@300cpu,arm,cortex-a55 psci*>K@]jw@ l3-cache,cache@M@_opp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc" protocol@14(opp-table-1,operating-points-v2Dopp-200000000   P PB@opp-300000000  P PB@opp-400000000ׄ  P PB@opp-600000000#F  B@opp-700000000)' ~~B@opp-800000000/ B@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codecsimple-audio-card,cpu pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0#smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24m(xin32k ,fixed-clockxin32kdefault(sram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob _ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob ` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBotg Jutmi_wide4SZokay usb2-phys zhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4SZokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(usb@fd800000 ,generic-ehci usbokayusb@fd840000 ,generic-ohci usbokayusb@fd880000 ,generic-ehci usb disabledusb@fd8c0000 ,generic-ohci usb disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd_io-domains&,rockchip,rk3568-pmu-io-voltage-domainokay &4Bsyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru(Pclock-controller@fdd20000,rockchip,rk3568-cruxin24m(P] mG  i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- i2cpclk!default okayregulator@1c ,tcs,tcs4525vdd_cpu 50+="regulator-state-memHpmic@20,rockchip,rk809 #]HmclkHrk808-clkout1rk808-clkout2default$%a(&&&&&&&&&regulatorsDCDC_REG1vdd_log+ pqregulator-state-mem % DCDC_REG2vdd_gpu+ pqEregulator-state-memH% DCDC_REG3vcc_ddr+Aregulator-state-mem DCDC_REG4vdd_npu pAregulator-state-memHDCDC_REG5vcc_1v8+w@w@regulator-state-mem %w@LDO_REG1vdda0v9_image+  [regulator-state-mem % LDO_REG2 vdda_0v9+  regulator-state-mem % LDO_REG3 vdda0v9_pmu+  regulator-state-mem % LDO_REG4 vccio_acodec+2Z2Zregulator-state-mem %2ZLDO_REG5 vccio_sd+w@2Zregulator-state-mem %2ZLDO_REG6 vcc3v3_pmu+2Z2Zregulator-state-mem %2ZLDO_REG7 vcca_1v8+w@w@regulator-state-mem %w@LDO_REG8 vcca1v8_pmu+w@w@regulator-state-mem %w@LDO_REG9vcca1v8_image+w@w@\regulator-state-mem %w@SWITCH_REG1+vcc_3v3SWITCH_REG2 vcc3v3_sdhserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,baudclkapb_pclkX''(default]j disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)defaultt disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk*defaultt disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk+defaultt disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk,defaultt disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller power-domain@7-power-domain@8 ./0power-domain@9  123power-domain@10 456789power-domain@11 :power-domain@13 ;power-domain@14 <=>power-domain@15?@ABCgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpugpubus *D4okayEvideo-codec@fdea0400,rockchip,rk3568-vpu vdpu aclkhclkF4 iommu@fdea0800,rockchip,rk3568-iommu@  aclkiface4 Frga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ZaclkhclksclkS&$% coreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepu @ aclkhclkG4 iommu@fdee0800,rockchip,rk3568-iommu@ ? aclkiface4 Gmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d biuciuciu-driveciu-sampleрSreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refS stmmaceth HI#J6okay]K?inputLrgmiiUdefaultLMNOPQ `Rp N O$Smdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22Sstmmac-axi-configHrx-queues-configIqueue0tx-queues-configJqueue0vop@fe040000 0@vopgamma-lut (%aclkhclkdclk_vp0dclk_vp1dclk_vp2T4  okay,rockchip,rk3566-vop]ports port@0 endpoint@2U]port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?  aclkiface4 okayTdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DpclkdphyV4 apbS  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi EpclkdphyW4 apbS  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -((iahbisfrcecrefdefault XYZ4 ] okay([8\ports port@0endpoint]Uport@1endpoint^qos@fe128000,rockchip,rk3568-qossyscon -qos@fe138080,rockchip,rk3568-qossyscon <qos@fe138100,rockchip,rk3568-qossyscon =qos@fe138180,rockchip,rk3568-qossyscon >qos@fe148000,rockchip,rk3568-qossyscon .qos@fe148080,rockchip,rk3568-qossyscon /qos@fe148100,rockchip,rk3568-qossyscon 0qos@fe150000,rockchip,rk3568-qossyscon :qos@fe158000,rockchip,rk3568-qossyscon 4qos@fe158100,rockchip,rk3568-qossyscon 5qos@fe158180,rockchip,rk3568-qossyscon 6qos@fe158200,rockchip,rk3568-qossyscon 7qos@fe158280,rockchip,rk3568-qossyscon 8qos@fe158300,rockchip,rk3568-qossyscon 9qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon ?qos@fe190280,rockchip,rk3568-qossyscon @qos@fe190300,rockchip,rk3568-qossyscon Aqos@fe190380,rockchip,rk3568-qossyscon Bqos@fe190400,rockchip,rk3568-qossyscon Cqos@fe198000,rockchip,rk3568-qossyscon ;qos@fe1a8000,rockchip,rk3568-qossyscon 1qos@fe1a8080,rockchip,rk3568-qossyscon 2qos@fe1a8100,rockchip,rk3568-qossyscon 3dfi@fe230000,rockchip,rk3568-dfi#  H_pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<KJIHGsyspmcmsglegacyerrU($aclk_mstaclk_slvaclk_dbipclkauxpci_`r```` pcie-phy4T @@Spipe okaydefaulta b clegacy-interrupt-controller H`mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b biuciuciu-driveciu-sampleрSresetokay # defaultdefg  (h 4mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c biuciuciu-driveciu-sampleрSresetokay A N di odefault jkl (& 4spi@fe300000 ,rockchip,sfc0@ exvclk_sfchclk_sfcmdefaultokay flash@0,jedec,spi-nor }n6  mmc@fe310000,rockchip,rk3568-dwcmshc1 ]{}m n6(|zy{}corebusaxiblocktimerokay  o ( 4i2s@fe400000,rockchip,rk3568-i2s-tdm@ 4]=AmFqFq?C9mclk_txmclk_rxhclkXn txSPQ tx-mrx-m okay i2s@fe410000,rockchip,rk3568-i2s-tdmA 5]EImFqFqGK:mclk_txmclk_rxhclkXnn rxtxSRS tx-mrx-m defaultopqrokay i2s@fe420000,rockchip,rk3568-i2s-tdmB 6]MmFqOO;mclk_txmclk_rxhclkXnn txrxSTtx-m defaultstuv disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7SW<mclk_txmclk_rxhclkXnn txrxSUV tx-mrx-m  disabledpdm@fe440000,rockchip,rk3568-pdmD LZYpdm_clkpdm_hclkXn  rxwxyz{|defaultSXpdm-m disabledspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk_\Xn txdefault} disableddma-controller@fe530000,arm,pl330arm,primecellS@    apb_pclk 'dma-controller@fe550000,arm,pl330arm,primecellU@   apb_pclk ni2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ /HG i2cpclk~default  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0JI i2cpclkdefault okayi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1LK i2cpclkdefault okayi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2NM i2cpclkdefault okayi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3PO i2cpclkdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia gRQspiclkapb_pclkX'' txrxdefault   disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib hTSspiclkapb_pclkX'' txrxdefault   disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic iVUspiclkapb_pclkX'' txrxdefault   disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid jXWspiclkapb_pclkX'' txrxdefault   disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte ubaudclkapb_pclkX'' default]jokay txrx bluetooth,brcm,bcm4345c5lpo #  +#  =#default  L& Xserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v# baudclkapb_pclkX''default]jokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w'$baudclkapb_pclkX''default]j disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x+(baudclkapb_pclkX'' default]j disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y/,baudclkapb_pclkX' ' default]j disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z30baudclkapb_pclkX' ' default]j disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk {74baudclkapb_pclkX''default]j disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl |;8baudclkapb_pclkX''default]j disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm }?<baudclkapb_pclkX''default]j disabledthermal-zonescpu-thermal ed { tripscpu_alert0 p passivecpu_alert1 $ passivecpu_crit s  criticalcooling-mapsmap0 0 gpu-thermal e { tripsgpu-threshold p passivegpu-target $ passivegpu-crit s  criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq s]mf@ `tsadcapb_pclkS  sdefaultsleep  okaysaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]saradcapb_pclkS saradc-apb okay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultt disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultt disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultt disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultt disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultt disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultt disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultt disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultt disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultt disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultt disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultt disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultt disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe]"mS  + Aokayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe]%mS  + Aokayphy@fe870000,rockchip,rk3568-csi-dphyypclk ASapb  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz A4 apbS disabledVmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ A4 apbS disabledWusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m  L(okayhost-port AokayUotg-port AokayUusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m  L(okayhost-port A disabledotg-port AokayUpinctrl,rockchip,rk3568-pinctrl H_ gpio@fdd60000,rockchip,gpio-bank !.  \ l  x#gpio@fe740000,rockchip,gpio-bankt "cd \ l  xbgpio@fe750000,rockchip,gpio-banku #ef \ l@  xgpio@fe760000,rockchip,gpio-bankv $gh \ l`  xRgpio@fe770000,rockchip,gpio-bankw %ij \ l  xpcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmceth0eth1flashfspifspi-pins` mgmac0gmac1gmac1m1-miim Lgmac1m1-clkinout Pgmac1m1-rx-bus20  Ngmac1m1-tx-bus20 Mgmac1m1-rgmii-clk Ogmac1m1-rgmii-bus@ Qgpuhdmitxhdmitxm0-cec Zhdmitx-scl Xhdmitx-sda Yi2c0i2c0-xfer  !i2c1i2c1-xfer  ~i2c2i2c2m1-xfer   i2c3i2c3m1-xfer  i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrcktx pi2s1m0-mclk %i2s1m0-sclktx oi2s1m0-sdi0  qi2s1m0-sdo0 ri2s2i2s2m0-lrcktx ti2s2m0-sclktx si2s2m0-sdi ui2s2m0-sdo vi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk wpdmm0-clk1 xpdmm0-sdi0  ypdmm0-sdi1  zpdmm0-sdi2  {pdmm0-sdi3 |pmicpmic_int $pmupwm0pwm0m0-pins )pwm1pwm1m0-pins *pwm2pwm2m0-pins +pwm3pwm3-pins ,pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ dsdmmc0-clk esdmmc0-cmd fsdmmc0-det gsdmmc1sdmmc1-bus4@ jsdmmc1-clk lsdmmc1-cmd ksdmmc2spdifspdifm0-tx }spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer (uart1uart1m0-xfer   uart1m0-ctsn uart1m0-rtsn  uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2btbt-enable-h bt-host-wake-l bt-wake-l ledsuser-led-enable-h pciepcie-enable-h pcie-reset-h  asdio-pwrseqwifi-enable-h usbvcc5v0-usb30-host-en_h vcc5v0-usb-otg-en_h chosen serial2:1500000n8external-gmac1-clock ,fixed-clocksY@ gmac1_clkin(Khdmi-con,hdmi-connectoraportendpoint^leds ,gpio-ledsled-user user-led on # heartbeatdefault sound,simple-audio-cardLi2s 5Analog RK809esimple-audio-card,cpusimple-audio-card,codecsdio-pwrseqokay,mmc-pwrseq-simple ext_clockdefault # ,d CLK@ivcc3v3-pcie-p-regulator,regulator-fixed V k#defaultvcc3v3_pcie_p2Z2Z=cvcc5v0-in-regulator,regulator-fixed vcc5v0_in+LK@LK@vcc5v0-sys-regulator,regulator-fixed vcc5v0_sys+LK@LK@="vcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z2Z="&vcc5v0-usb30-host-regulator,regulator-fixedvcc5v0_usb30_host V k#defaultLK@LK@="vcc5v0-usb-otg-regulator,regulator-fixedvcc5v0_usb_otg V k#defaultLK@LK@=" interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendrockchip,system-power-controller#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-on-in-suspendregulator-suspend-microvoltregulator-initial-modedmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr50vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablespi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedpost-power-on-delay-mspower-off-delay-usenable-active-high