8( "̨ =,xunlong,orangepi-3b-v1.1xunlong,orangepi-3brockchip,rk35667Xunlong Orange Pi 3B v1.1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe310000/mmc@fe2b0000/mmc@fe2c0000cpus cpu@0cpu,arm,cortex-a55 psci*>K@]jw@ cpu@100cpu,arm,cortex-a55 psci*>K@]jw@ cpu@200cpu,arm,cortex-a55 psci*>K@]jw@ cpu@300cpu,arm,cortex-a55 psci*>K@]jw@ l3-cache,cache@M@_opp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc" protocol@14(opp-table-1,operating-points-v2Bopp-200000000   P PB@opp-300000000  P PB@opp-400000000ׄ  P PB@opp-600000000#F  B@opp-700000000)' ~~B@opp-800000000/ B@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codecsimple-audio-card,cpu pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0#smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24m(xin32k ,fixed-clockxin32kdefault(sram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob _ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob ` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBhost Jutmi_wide4SZokay usb2-phys zhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4SZokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(usb@fd800000 ,generic-ehci usbokayusb@fd840000 ,generic-ohci usbokayusb@fd880000 ,generic-ehci usbokayusb@fd8c0000 ,generic-ohci usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd\io-domains&,rockchip,rk3568-pmu-io-voltage-domainokay &4Bsyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru(Pclock-controller@fdd20000,rockchip,rk3568-cruxin24m(P] mG i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- i2cpclk default okaypmic@20,rockchip,rk809 ]H(Hmclkrk809-clkout1rk809-clkout2!default"#$$$$ $$%$1$=$regulatorsDCDC_REG1 Ivdd_logicXl~ pqregulator-state-memDCDC_REG2Ivdd_gpuXl~ pqCregulator-state-memDCDC_REG3Ivcc_ddrXl~regulator-state-memDCDC_REG4Ivdd_npu~ pqregulator-state-memDCDC_REG5Ivcc_1v8Xlw@w@regulator-state-memLDO_REG1Ivdda0v9_image  Xregulator-state-memLDO_REG2 Ivdda_0v9Xl  regulator-state-memLDO_REG3 Ivdda0v9_pmuXl  regulator-state-mem LDO_REG4 Ivccio_acodecXl2Z2Zregulator-state-memLDO_REG5 Ivccio_sdXlw@2Zregulator-state-memLDO_REG6 Ivcc3v3_pmuXl2Z2Zregulator-state-mem 2ZLDO_REG7 Ivcca_1v8Xlw@w@regulator-state-memLDO_REG8 Ivcca1v8_pmuXlw@w@regulator-state-mem w@LDO_REG9Ivcca1v8_imagew@w@Yregulator-state-memSWITCH_REG1Ivcc_3v3Xlregulator-state-memSWITCH_REG2 Ivcc3v3_sdXldregulator-state-memregulator@40,silergy,syr827@'Ivdd_cpuXl 0OD$regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,baudclkapb_pclkO%%&defaultTa disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk'defaultk disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(defaultk disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)defaultk disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk*defaultk disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllerv power-domain@7+vpower-domain@8 ,-.vpower-domain@9  /01vpower-domain@10 234567vpower-domain@11 8vpower-domain@13 9vpower-domain@14 :;<vpower-domain@15=>?@Avgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpugpubus *B4okayCvideo-codec@fdea0400,rockchip,rk3568-vpu vdpu aclkhclkD4 iommu@fdea0800,rockchip,rk3568-iommu@  aclkiface4 Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ZaclkhclksclkS&$% coreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepu @ aclkhclkE4 iommu@fdee0800,rockchip,rk3568-iommu@ ? aclkiface4 Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d biuciuciu-driveciu-sampleрSreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refS stmmacethFGH-okay]6input Crgmii-idLdefaultIJKLMNWOmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22bN rP POstmmac-axi-configFrx-queues-configGqueue0tx-queues-configHqueue0vop@fe040000 0@vopgamma-lut (%aclkhclkdclk_vp0dclk_vp1dclk_vp2Q4 okay,rockchip,rk3566-vop]ports port@0 endpoint@2RZport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?  aclkiface4 okayQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DpclkdphyS4 apbS disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi EpclkdphyT4 apbS disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -((iahbisfrcecrefdefault UVW4 TokayXYports port@0endpointZRport@1endpoint[qos@fe128000,rockchip,rk3568-qossyscon +qos@fe138080,rockchip,rk3568-qossyscon :qos@fe138100,rockchip,rk3568-qossyscon ;qos@fe138180,rockchip,rk3568-qossyscon <qos@fe148000,rockchip,rk3568-qossyscon ,qos@fe148080,rockchip,rk3568-qossyscon -qos@fe148100,rockchip,rk3568-qossyscon .qos@fe150000,rockchip,rk3568-qossyscon 8qos@fe158000,rockchip,rk3568-qossyscon 2qos@fe158100,rockchip,rk3568-qossyscon 3qos@fe158180,rockchip,rk3568-qossyscon 4qos@fe158200,rockchip,rk3568-qossyscon 5qos@fe158280,rockchip,rk3568-qossyscon 6qos@fe158300,rockchip,rk3568-qossyscon 7qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon =qos@fe190280,rockchip,rk3568-qossyscon >qos@fe190300,rockchip,rk3568-qossyscon ?qos@fe190380,rockchip,rk3568-qossyscon @qos@fe190400,rockchip,rk3568-qossyscon Aqos@fe198000,rockchip,rk3568-qossyscon 9qos@fe1a8000,rockchip,rk3568-qossyscon /qos@fe1a8080,rockchip,rk3568-qossyscon 0qos@fe1a8100,rockchip,rk3568-qossyscon 1dfi@fe230000,rockchip,rk3568-dfi#   \pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<KJIHGsyspmcmsglegacyerr-($aclk_mstaclk_slvaclk_dbipclkauxpci7`J]]]]Xix pcie-phy4T @@Spipe okaydefault^ !_legacy-interrupt-controller H]mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b biuciuciu-driveciu-sampleрSresetokaydefault`abcdmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c biuciuciu-driveciu-sampleрSresetokay  e % , 2default fgh @spi@fe300000 ,rockchip,sfc0@ exvclk_sfchclk_sfcidefaultokay flash@0,jedec,spi-nor N2 ` qmmc@fe310000,rockchip,rk3568-dwcmshc1 ]{}m n6(|zy{}corebusaxiblocktimerokay    2defaultjklmi2s@fe400000,rockchip,rk3568-i2s-tdm@ 4]=AmFqFq?C9mclk_txmclk_rxhclkOn txSPQ tx-mrx-mokay i2s@fe410000,rockchip,rk3568-i2s-tdmA 5]EImFqFqGK:mclk_txmclk_rxhclkOnn rxtxSRS tx-mrx-mdefaultopqrokay i2s@fe420000,rockchip,rk3568-i2s-tdmB 6]MmFqOO;mclk_txmclk_rxhclkOnn txrxSTtx-mdefaultstuv disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7SW<mclk_txmclk_rxhclkOnn txrxSUV tx-mrx-m disabledpdm@fe440000,rockchip,rk3568-pdmD LZYpdm_clkpdm_hclkOn  rxwxyz{|defaultSXpdm-m disabledspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk_\On txdefault} disableddma-controller@fe530000,arm,pl330arm,primecellS@    apb_pclk %dma-controller@fe550000,arm,pl330arm,primecellU@   apb_pclk ni2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ /HG i2cpclk~default  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0JI i2cpclkdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1LK i2cpclkdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2NM i2cpclkdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3PO i2cpclkdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia gRQspiclkapb_pclkO%% txrxdefault   disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib hTSspiclkapb_pclkO%% txrxdefault   disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic iVUspiclkapb_pclkO%% txrxdefault   disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid jXWspiclkapb_pclkO%% txrxdefault   disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte ubaudclkapb_pclkO%% defaultTaokay serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v# baudclkapb_pclkO%%defaultTaokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w'$baudclkapb_pclkO%%defaultTa disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x+(baudclkapb_pclkO%% defaultTa disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y/,baudclkapb_pclkO% % defaultTa disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z30baudclkapb_pclkO% % defaultTa disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk {74baudclkapb_pclkO%%defaultTa disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl |;8baudclkapb_pclkO%%defaultTa disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm }?<baudclkapb_pclkO%%defaultTa disabledthermal-zonescpu-thermal d  tripscpu_alert0 .p :passivecpu_alert1 .$ :passivecpu_crit .s : criticalcooling-mapsmap0 E0 J gpu-thermal   tripsgpu-threshold .p :passivegpu-target .$ :passivegpu-crit .s : criticalcooling-mapsmap0 E Jtsadc@fe710000,rockchip,rk3568-tsadcq s]mf@ `tsadcapb_pclkS Ysdefaultsleep p zokay  saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]saradcapb_pclkS saradc-apb okay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultk disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultk disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultk disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultk disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultk disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultk disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultk disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultk disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultk disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultk disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultk disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultk disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe]"mS   okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe]%mS   okayphy@fe870000,rockchip,rk3568-csi-dphyypclk Sapb disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz 4 apbS disabledSmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ 4 apbS disabledTusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m  (okayhost-port okayLotg-port okayLusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m  (okayhost-port okayLotg-port okayLpinctrl,rockchip,rk3568-pinctrl \ gpio@fdd60000,rockchip,gpio-bank !.  # 3  ?!gpio@fe740000,rockchip,gpio-bankt "cd # 3  ?gpio@fe750000,rockchip,gpio-banku #ef # 3@  ?gpio@fe760000,rockchip,gpio-bankv $gh # 3`  ?Pgpio@fe770000,rockchip,gpio-bankw %ij # 3  ?pcfg-pull-up Kpcfg-pull-down Xpcfg-pull-none gpcfg-pull-none-drv-level-1 g tpcfg-pull-none-drv-level-2 g tpcfg-pull-none-drv-level-3 g tpcfg-pull-up-drv-level-1 K tpcfg-pull-up-drv-level-2 K tpcfg-pull-none-smt g acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmcemmc-bus8   jemmc-clk kemmc-cmd lemmc-datastrobe meth0eth1flashfspifspi-pins` igmac0gmac1gmac1m0-miim Igmac1m0-clkinout Ngmac1m0-rx-bus20    Kgmac1m0-tx-bus20  Jgmac1m0-rgmii-clk Lgmac1m0-rgmii-bus@ Mgpuhdmitxhdmitxm0-cec Whdmitx-scl Uhdmitx-sda Vi2c0i2c0-xfer   i2c1i2c1-xfer  ~i2c2i2c2m0-xfer i2c3i2c3m0-xfer i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrcktx pi2s1m0-mclk #i2s1m0-sclktx oi2s1m0-sdi0  qi2s1m0-sdo0 ri2s2i2s2m0-lrcktx ti2s2m0-sclktx si2s2m0-sdi ui2s2m0-sdo vi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk wpdmm0-clk1 xpdmm0-sdi0  ypdmm0-sdi1  zpdmm0-sdi2  {pdmm0-sdi3 |pmicpmic-int-l "pmupwm0pwm0m0-pins 'pwm1pwm1m0-pins (pwm2pwm2m0-pins )pwm3pwm3-pins *pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ `sdmmc0-clk asdmmc0-cmd bsdmmc0-det csdmmc1sdmmc1-bus4@ fsdmmc1-clk gsdmmc1-cmd hsdmmc2spdifspdifm0-tx }spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer &uart1uart1m0-xfer   uart1m0-ctsn uart1m0-rtsn  uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2bluetoothbt-reg-on-h bt-wake-host-h host-wake-bt-h ledswork-led pciepcie20-pins0  ^pcie20-pwren usbusb-host-pwren-h usb-otg-pwren-h wifiwifi-reg-on-h wifi-wake-host-h chosen serial2:1500000n8hdmi-con,hdmi-connectoraportendpoint[leds ,gpio-ledsdefaultled-0  on heartbeat ! heartbeatregulator-3v3-vcc-pcie30,regulator-fixed  !defaultIvcc3v3_pcie302Z2ZD$_regulator-3v3-vcc-sys,regulator-fixed Ivcc3v3_sysXl2Z2ZD$regulator-5v0-vcc-sys,regulator-fixed Ivcc5v0_sysXlLK@LK@regulator-5v0-vcc-usb-host,regulator-fixed  !defaultIvcc5v0_usb_hostLK@LK@Dregulator-5v0-vcc-usb-otg,regulator-fixed  !defaultIvcc5v0_usb_otgLK@LK@Dsdio-pwrseq,mmc-pwrseq-simple ext_clockdefault  LK@ !esound,simple-audio-cardLi2s 5Analog RK809esimple-audio-card,cpusimple-audio-card,codec interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio6-supplyvccio7-supplyvccio5-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplyphy-handlereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr104spi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthcap-mmc-highspeedmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathcolordefault-statefunctionlinux,default-triggerenable-active-highpost-power-on-delay-mspower-off-delay-us