`8\8(\renesas,v3mskrenesas,r8a77970 &Renesas V3M Starter Kit boardaliases,/soc/i2c@e65000001/soc/i2c@e65080006/soc/i2c@e6510000;/soc/i2c@e66d0000@/soc/i2c@e66d8000E/soc/serial@e6e60000can fixed-clockMZjcpus cpu@0rcpuarm,cortex-a53~ pscijcpu@1rcpuarm,cortex-a53~ pscijcache-controllercachejextal fixed-clockMZP*jextalr fixed-clockMZj pmu_a53arm,cortex-a53-pmu TUpsciarm,psci-1.0arm,psci-0.2smcscif fixed-clockMZjsoc simple-bus watchdog@e6020000+renesas,r8a77970-wdtrenesas,rcar-gen3-wdt~    disabledgpio@e6050000-renesas,gpio-r8a77970renesas,rcar-gen3-gpio~P (4DPa  gpio@e6051000-renesas,gpio-r8a77970renesas,rcar-gen3-gpio~P (4D Pa  j gpio@e6052000-renesas,gpio-r8a77970renesas,rcar-gen3-gpio~ P (4D@Pa  gpio@e6053000-renesas,gpio-r8a77970renesas,rcar-gen3-gpio~0P (4D`Pa  gpio@e6054000-renesas,gpio-r8a77970renesas,rcar-gen3-gpio~@P (4DPa  gpio@e6055000-renesas,gpio-r8a77970renesas,rcar-gen3-gpio~PP  (4DPa  pin-controller@e6060000renesas,pfc-r8a77970~javb0$vavb0_mdioavb0_rgmiiavb0_txcrefclk}avb0ji2c0vi2c0}i2c0j mmc_3_3vvmmc_data8mmc_ctrl}mmc jscif0 vscif0_data}scif0jtimer@e60f0000-renesas,r8a77970-cmt0renesas,rcar-gen3-cmt0~ /fck / disabledtimer@e6130000-renesas,r8a77970-cmt1renesas,rcar-gen3-cmt1~`xyz{|}~ .fck . disabledtimer@e6140000-renesas,r8a77970-cmt1renesas,rcar-gen3-cmt1~`  -fck - disabledtimer@e6148000-renesas,r8a77970-cmt1renesas,rcar-gen3-cmt1~` ,fck , disabledclock-controller@e6150000renesas,r8a77970-cpg-mssr~  extalextalrMjreset-controller@e6160000renesas,r8a77970-rst~system-controller@e6180000renesas,r8a77970-sysc~@jthermal@e6190000renesas,thermal-r8a77970 ~ $CDE    j*interrupt-controller@e61c0000&renesas,intc-ex-r8a77970renesas,irqcPa~H  timer@e61e0000!renesas,tmu-r8a77970renesas,tmu~0$ }fck } disabledtimer@e6fc0000!renesas,tmu-r8a77970renesas,tmu~0$ |fck | disabledtimer@e6fd0000!renesas,tmu-r8a77970renesas,tmu~0$/01 {fck { disabledtimer@e6fe0000!renesas,tmu-r8a77970renesas,tmu~0$ zfck z disabledtimer@ffc00000!renesas,tmu-r8a77970renesas,tmu~0$tuv yfck y disabledi2c@e6500000+renesas,i2c-r8a77970renesas,rcar-gen3-i2c~P@      txrxtxrx okay  defaultZhdmi@39 adi,adv7511w~9 (4@LYhxrgb1xevenlyports port@0~endpointj-port@1~endpointj+i2c@e6508000+renesas,i2c-r8a77970renesas,rcar-gen3-i2c~P@       txrxtxrx  disabledi2c@e6510000+renesas,i2c-r8a77970renesas,rcar-gen3-i2c~Q@      txrxtxrx  disabledi2c@e66d0000+renesas,i2c-r8a77970renesas,rcar-gen3-i2c~m@ "     txrxtxrx  disabledi2c@e66d8000+renesas,i2c-r8a77970renesas,rcar-gen3-i2c~m@      txrxtxrx  disabledserial@e6540000=renesas,hscif-r8a77970renesas,rcar-gen3-hscifrenesas,hscif~T`  fckbrg_intscif_clk  1 0 1 0 txrxtxrx  disabledserial@e6550000=renesas,hscif-r8a77970renesas,rcar-gen3-hscifrenesas,hscif~U`  fckbrg_intscif_clk  3 2 3 2 txrxtxrx  disabledserial@e6560000=renesas,hscif-r8a77970renesas,rcar-gen3-hscifrenesas,hscif~V`  fckbrg_intscif_clk  5 4 5 4 txrxtxrx  disabledserial@e66a0000=renesas,hscif-r8a77970renesas,rcar-gen3-hscifrenesas,hscif~j`  fckbrg_intscif_clk  7 6 7 6 txrxtxrx  disabledcan@e66c0000/renesas,r8a77970-canfdrenesas,rcar-gen3-canfd~lfckcanfdcan_clk bZ  disabledchannel0 disabledchannel1 disabledethernet@e68000005renesas,etheravb-r8a77970renesas,etheravb-rcar-gen3~,'()*+,-./0123456789:;<=>?sch0ch1ch2ch3ch4ch5ch6ch7ch8ch9ch10ch11ch12ch13ch14ch15ch16ch17ch18ch19ch20ch21ch22ch23ch24 , ,  rgmii-id okay default0ethernet-phy@0;~ jpwm@e6e30000&renesas,pwm-r8a77970renesas,pwm-rcar~G     disabledpwm@e6e31000&renesas,pwm-r8a77970renesas,pwm-rcar~G     disabledpwm@e6e32000&renesas,pwm-r8a77970renesas,pwm-rcar~ G     disabledpwm@e6e33000&renesas,pwm-r8a77970renesas,pwm-rcar~0G     disabledpwm@e6e34000&renesas,pwm-r8a77970renesas,pwm-rcar~@G     disabledserial@e6e60000:renesas,scif-r8a77970renesas,rcar-gen3-scifrenesas,scif~@  fckbrg_intscif_clk  Q P Q P txrxtxrx okay defaultserial@e6e68000:renesas,scif-r8a77970renesas,rcar-gen3-scifrenesas,scif~@  fckbrg_intscif_clk  S R S R txrxtxrx  disabledserial@e6c50000:renesas,scif-r8a77970renesas,rcar-gen3-scifrenesas,scif~@  fckbrg_intscif_clk  W V W V txrxtxrx  disabledserial@e6c40000:renesas,scif-r8a77970renesas,rcar-gen3-scifrenesas,scif~@  fckbrg_intscif_clk  Y X Y X txrxtxrx  disabledpwm@e6e80000!renesas,tpu-r8a77970renesas,tpu~H  0 0G disabledspi@e6e90000/renesas,msiof-r8a77970renesas,rcar-gen3-msiof~d     A @ A @ txrxtxrx  disabledspi@e6ea0000/renesas,msiof-r8a77970renesas,rcar-gen3-msiof~d     C B C B txrxtxrx  disabledspi@e6c00000/renesas,msiof-r8a77970renesas,rcar-gen3-msiof~d     E D E D txrxtxrx  disabledspi@e6c10000/renesas,msiof-r8a77970renesas,rcar-gen3-msiof~d     G F G F txrxtxrx  disabledvideo@e6ef0000renesas,vin-r8a77970~  + +R disabledports port@1 ~endpoint@2~j!video@e6ef1000renesas,vin-r8a77970~  * *R disabledports port@1 ~endpoint@2~j"video@e6ef2000renesas,vin-r8a77970~   ) )R disabledports port@1 ~endpoint@2~j#video@e6ef3000renesas,vin-r8a77970~0  ( (R disabledports port@1 ~endpoint@2~j$dma-controller@e7300000(renesas,dmac-r8a77970renesas,rcar-dmac~0l4567&errorch0ch1ch2ch3ch4ch5ch6ch7 fck ]h@j dma-controller@e7310000(renesas,dmac-r8a77970renesas,rcar-dmac~1l389:;<=>?&errorch0ch1ch2ch3ch4ch5ch6ch7 fck ]h@j mmu@e7740000renesas,ipmmu-r8a77970~tu jmmu@ff8b0000renesas,ipmmu-r8a77970~ummu@e67b0000renesas,ipmmu-r8a77970~{ jmmu@ffc80000renesas,ipmmu-r8a77970~u jmmu@febd0000renesas,ipmmu-r8a77970~u  mmc@ee140000-renesas,sdhi-r8a77970renesas,rcar-gen3-sdhi~   : : okay defaultinterrupt-controller@f1010000 arm,gic-400P a@~   clk jvsp@fea20000 renesas,vsp2~P  o o j&fcp@fea27000 renesas,fcpv~p [ [j csi2@feaa0000renesas,r8a77970-csi2~    disabledports port@1 ~endpoint@0~!jendpoint@1~"jendpoint@2~#jendpoint@3~$jdisplay@feb00000renesas,du-r8a77970~ %du.0dclkin.0 &okayports port@0~endpointport@1~endpoint'j(lvds-encoder@feb90000renesas,r8a77970-lvds~  okayports port@0~endpoint(j'port@1~endpoint)j,chipid@fff00044 renesas,prr~Dthermal-zonescpu-thermal *cooling-mapstripscpu-crit% ycriticaltimerarm,armv8-timer@   chosen0serial0:115200n8hdmi-outhdmi-connectoryaportendpoint+jlvds-decoderthine,thc63lvd1024<ports port@0~endpoint,j)port@2~endpoint-jmemory@48000000rmemory~H8osc5-clock fixed-clockMZ j%regulator-0regulator-fixed GVCC_D1.8VVw@nw@jregulator-1regulator-fixed GVCC_D3.3VV2Zn2Zjregulator-2regulator-fixedGVCC_VDDQ_VIN0V2Zn2Zj compatible#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4serial0#clock-cellsclock-frequencyphandledevice_typeregclockspower-domainsnext-level-cacheenable-methodcache-unifiedcache-levelinterrupts-extendedinterrupt-affinityinterrupt-parentrangesresetsstatusinterrupts#gpio-cellsgpio-controllergpio-ranges#interrupt-cellsinterrupt-controllergroupsfunctionpower-sourceclock-names#power-domain-cells#reset-cells#thermal-sensor-cellsdmasdma-namesi2c-scl-internal-delay-nspinctrl-0pinctrl-names#sound-dai-cellsavdd-supplydvdd-supplypvdd-supplybgvdd-supplydvdd-3v-supplyadi,input-depthadi,input-colorspaceadi,input-clockadi,input-styleadi,input-justificationremote-endpointassigned-clocksassigned-clock-ratesinterrupt-namesphy-modeiommusrenesas,no-ether-linkphy-handlerxc-skew-ps#pwm-cellsrenesas,id#dma-cellsdma-channelsrenesas,ipmmu-main#iommu-cellsmax-frequencyvmmc-supplyvqmmc-supplybus-widthnon-removablerenesas,fcpvspspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresisstdout-pathvcc-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-on