8θ( D΀ =,xunlong,orangepi-3b-v1.1xunlong,orangepi-3brockchip,rk35667Xunlong Orange Pi 3B v1.1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe310000/mmc@fe2b0000/mmc@fe2c0000cpus cpu@0cpu,arm,cortex-a55 psci*7@IVc@u cpu@100cpu,arm,cortex-a55 psci*7@IVc@u cpu@200cpu,arm,cortex-a55 psci*7@IVc@u cpu@300cpu,arm,cortex-a55 psci*7@IVc@u l3-cache,cache,9@Kdisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smcڂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s(Bokaysimple-audio-card,codecIsimple-audio-card,cpuI pmu,arm,cortex-a55-pmu0S^ psci ,arm,psci-1.0#smcreserved-memory qshmem@10f000,arm,scmi-shmemxtimer,arm,armv8-timer0S   xin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob S_ sata-phy Bdisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob S` sata-phy Bdisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Sref_clksuspend_clkbus_clk host utmi_wide$Bokay usb2-phy= Dhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Sref_clksuspend_clkbus_clk host usb2-phyusb3-phy utmi_wide$Bokayinterrupt-controller@fd400000 ,arm,gic-v3 @F S RgxA(q msi-controller@fd440000,arm,gic-v3-itsD^usb@fd800000 ,generic-ehci SusbBokayusb@fd840000 ,generic-ohci SusbBokayusb@fd880000 ,generic-ehci SusbBokayusb@fd8c0000 ,generic-ohci SusbBokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd\io-domains&,rockchip,rk3568-pmu-io-voltage-domainBokay 'syscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru5clock-controller@fdd20000,rockchip,rk3568-cruxin24m5B RG g~i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c S.- i2cpclk default Bokaypmic@20,rockchip,rk809 BHgHmclkrk809-clkout1rk809-clkout2!Sdefault"#$$$$$$ $$"$regulatorsDCDC_REG1 .vdd_logic=Qcz pqregulator-state-memDCDC_REG2.vdd_gpu=Qcz pqCregulator-state-memDCDC_REG3.vcc_ddr=Qcregulator-state-memDCDC_REG4.vdd_npucz pqregulator-state-memDCDC_REG5.vcc_1v8=Qzw@w@regulator-state-memLDO_REG1.vdda0v9_imagez  Xregulator-state-memLDO_REG2 .vdda_0v9=Qz  regulator-state-memLDO_REG3 .vdda0v9_pmu=Qz  regulator-state-mem LDO_REG4 .vccio_acodec=Qz2Z2Zregulator-state-memLDO_REG5 .vccio_sd=Qzw@2Zregulator-state-memLDO_REG6 .vcc3v3_pmu=Qz2Z2Zregulator-state-mem2ZLDO_REG7 .vcca_1v8=Qzw@w@regulator-state-memLDO_REG8 .vcca1v8_pmu=Qzw@w@regulator-state-memw@LDO_REG9.vcca1v8_imagezw@w@Yregulator-state-memSWITCH_REG1.vcc_3v3=Qregulator-state-memSWITCH_REG2 .vcc3v3_sd=Qeregulator-state-memregulator@40,silergy,syr827@ .vdd_cpu=Qz 0O)$regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart St ,baudclkapb_pclk4%%&default9F Bdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk'defaultP Bdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(defaultP Bdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)defaultP Bdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk*defaultP Bdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller[ power-domain@7o+[power-domain@8 o,-.[power-domain@9  o/01[power-domain@10 o234567[power-domain@11 o8[power-domain@13 o9[power-domain@14 o:;<[power-domain@15o=>?@A[gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$S()' vjobmmugpugpubus BokayBCvideo-codec@fdea0400,rockchip,rk3568-vpu Svvdpu aclkhclkD iommu@fdea0800,rockchip,rk3568-iommu@ S aclkiface Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga SZaclkhclksclk&$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu S@ aclkhclkE iommu@fdee0800,rockchip,rk3568-iommu@ S? aclkiface Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Sd biuciuciu-driveciu-sampleрreset Bdisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aS vmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref stmmaceth~FGHBokayBginput (rgmii-id1defaultIJKLMN<Omdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22GN WP iPOstmmac-axi-configuFrx-queues-configGqueue0tx-queues-configHqueue0vop@fe040000 0@vopgamma-lut S(%aclkhclkdclk_vp0dclk_vp1dclk_vp2Q ~Bokay,rockchip,rk3566-vopBgports port@0 endpoint@2RZport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? S aclkiface BokayQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi SDpclkdphyS apb~ Bdisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi SEpclkdphyT apb~ Bdisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  S-((iahbisfrcecrefdefault UVW 9~BokayXYports port@0endpointZRport@1endpoint[qos@fe128000,rockchip,rk3568-qossyscon +qos@fe138080,rockchip,rk3568-qossyscon :qos@fe138100,rockchip,rk3568-qossyscon ;qos@fe138180,rockchip,rk3568-qossyscon <qos@fe148000,rockchip,rk3568-qossyscon ,qos@fe148080,rockchip,rk3568-qossyscon -qos@fe148100,rockchip,rk3568-qossyscon .qos@fe150000,rockchip,rk3568-qossyscon 8qos@fe158000,rockchip,rk3568-qossyscon 2qos@fe158100,rockchip,rk3568-qossyscon 3qos@fe158180,rockchip,rk3568-qossyscon 4qos@fe158200,rockchip,rk3568-qossyscon 5qos@fe158280,rockchip,rk3568-qossyscon 6qos@fe158300,rockchip,rk3568-qossyscon 7qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon =qos@fe190280,rockchip,rk3568-qossyscon >qos@fe190300,rockchip,rk3568-qossyscon ?qos@fe190380,rockchip,rk3568-qossyscon @qos@fe190400,rockchip,rk3568-qossyscon Aqos@fe198000,rockchip,rk3568-qossyscon 9qos@fe1a8000,rockchip,rk3568-qossyscon /qos@fe1a8080,rockchip,rk3568-qossyscon 0qos@fe1a8100,rockchip,rk3568-qossyscon 1dfi@fe230000,rockchip,rk3568-dfi# S \pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<SKJIHGvsyspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpcig`/]]]]=N]l{^ pcie-phyTq @@pipe Bokaydefault_ i!`legacy-interrupt-controllergR SH]mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Sb biuciuciu-driveciu-sampleрresetBokaydefaultabcdemmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Sc biuciuciu-driveciu-sampleрresetBokayf   default ghi %spi@fe300000 ,rockchip,sfc0@ Sexvclk_sfchclk_sfcjdefaultBokay flash@0,jedec,spi-nor 32 E Vmmc@fe310000,rockchip,rk3568-dwcmshc1 SB{}R n6(|zy{}corebusaxiblocktimerBokay g  y defaultklmnrng@fe388000,rockchip,rk3568-rng8@po coreahbm Bdisabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ S4B=ARFqFq?C9mclk_txmclk_rxhclk4o txPQ tx-mrx-m~Bokay i2s@fe410000,rockchip,rk3568-i2s-tdmA S5BEIRFqFqGK:mclk_txmclk_rxhclk4oo rxtxRS tx-mrx-m~defaultpqrsBokay i2s@fe420000,rockchip,rk3568-i2s-tdmB S6BMRFqOO;mclk_txmclk_rxhclk4oo txrxTtx-m~defaulttuvw Bdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmC S7SW<mclk_txmclk_rxhclk4oo txrxUV tx-mrx-m~ Bdisabledpdm@fe440000,rockchip,rk3568-pdmD SLZYpdm_clkpdm_hclk4o  rxxyz{|}defaultXpdm-m Bdisabledspdif@fe460000,rockchip,rk3568-spdifF Sf mclkhclk_\4o txdefault~ Bdisableddma-controller@fe530000,arm,pl330arm,primecellS@S    apb_pclk %dma-controller@fe550000,arm,pl330arm,primecellU@S   apb_pclk oi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ S/HG i2cpclkdefault  Bdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ S0JI i2cpclkdefault  Bdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ S1LK i2cpclkdefault  Bdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] S2NM i2cpclkdefault  Bdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ S3PO i2cpclkdefault  Bdisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` S tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia SgRQspiclkapb_pclk4%% txrxdefault   Bdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib ShTSspiclkapb_pclk4%% txrxdefault   Bdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic SiVUspiclkapb_pclk4%% txrxdefault   Bdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid SjXWspiclkapb_pclk4%% txrxdefault   Bdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Subaudclkapb_pclk4%% default9FBokay serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Sv# baudclkapb_pclk4%%default9FBokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Sw'$baudclkapb_pclk4%%default9F Bdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Sx+(baudclkapb_pclk4%% default9F Bdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Sy/,baudclkapb_pclk4% % default9F Bdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Sz30baudclkapb_pclk4% % default9F Bdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk S{74baudclkapb_pclk4%%default9F Bdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl S|;8baudclkapb_pclk4%%default9F Bdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm S}?<baudclkapb_pclk4%%default9F Bdisabledthermal-zonescpu-thermal d  tripscpu_alert0 p passivecpu_alert1 $ passivecpu_crit s  criticalcooling-mapsmap0 *0 / gpu-thermal   tripsgpu-threshold p passivegpu-target $ passivegpu-crit s  criticalcooling-mapsmap0 * /tsadc@fe710000,rockchip,rk3568-tsadcq SsBRf@ `tsadcapb_pclk~ >sdefaultsleep U _Bokay u saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr S]saradcapb_pclk saradc-apb Bokay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultP Bdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultP Bdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultP Bdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultP Bdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultP Bdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultP Bdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultP Bdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultP Bdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultP Bdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultP Bdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultP Bdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultP Bdisabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipeB"Rphy   Bokayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipeB%Rphy   Bokayphy@fe870000,rockchip,rk3568-csi-dphyypclk apb~ Bdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz  apb BdisabledSmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{  apb BdisabledTusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m S Bokayhost-port Bokay1otg-port Bokay1usb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m S Bokayhost-port Bokay1otg-port Bokay1pinctrl,rockchip,rk3568-pinctrl~\ qgpio@fdd60000,rockchip,gpio-bank S!.     $Rg!gpio@fe740000,rockchip,gpio-bankt S"cd    $Rggpio@fe750000,rockchip,gpio-banku S#ef  @  $Rggpio@fe760000,rockchip,gpio-bankv S$gh  `  $RgPgpio@fe770000,rockchip,gpio-bankw S%ij    $Rgpcfg-pull-up 0pcfg-pull-down =pcfg-pull-none Lpcfg-pull-none-drv-level-1 L Ypcfg-pull-none-drv-level-2 L Ypcfg-pull-none-drv-level-3 L Ypcfg-pull-up-drv-level-1 0 Ypcfg-pull-up-drv-level-2 0 Ypcfg-pull-none-smt L hacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 }cpuebcedpdpemmcemmc-bus8 }  kemmc-clk }lemmc-cmd }memmc-datastrobe }neth0eth1flashfspifspi-pins` }jgmac0gmac1gmac1m0-miim }Igmac1m0-clkinout }Ngmac1m0-rx-bus20 }   Kgmac1m0-tx-bus20 } Jgmac1m0-rgmii-clk }Lgmac1m0-rgmii-bus@ }Mgpuhdmitxhdmitxm0-cec }Whdmitx-scl }Uhdmitx-sda }Vi2c0i2c0-xfer }   i2c1i2c1-xfer }  i2c2i2c2m0-xfer } i2c3i2c3m0-xfer }i2c4i2c4m0-xfer }  i2c5i2c5m0-xfer }  i2s1i2s1m0-lrcktx }qi2s1m0-mclk }#i2s1m0-sclktx }pi2s1m0-sdi0 } ri2s1m0-sdo0 }si2s2i2s2m0-lrcktx }ui2s2m0-sclktx }ti2s2m0-sdi }vi2s2m0-sdo }wi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk }xpdmm0-clk1 }ypdmm0-sdi0 } zpdmm0-sdi1 } {pdmm0-sdi2 } |pdmm0-sdi3 }}pmicpmic-int-l }"pmupwm0pwm0m0-pins }'pwm1pwm1m0-pins }(pwm2pwm2m0-pins })pwm3pwm3-pins }*pwm4pwm4-pins }pwm5pwm5-pins }pwm6pwm6-pins }pwm7pwm7-pins }pwm8pwm8m0-pins } pwm9pwm9m0-pins } pwm10pwm10m0-pins } pwm11pwm11m0-pins }pwm12pwm12m0-pins }pwm13pwm13m0-pins }pwm14pwm14m0-pins }pwm15pwm15m0-pins }refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ }asdmmc0-clk }bsdmmc0-cmd }csdmmc0-det }dsdmmc1sdmmc1-bus4@ }gsdmmc1-clk }hsdmmc1-cmd }isdmmc2spdifspdifm0-tx }~spi0spi0m0-pins0 } spi0m0-cs0 }spi0m0-cs1 }spi1spi1m0-pins0 } spi1m0-cs0 }spi1m0-cs1 }spi2spi2m0-pins0 }spi2m0-cs0 }spi2m0-cs1 }spi3spi3m0-pins0 }  spi3m0-cs0 }spi3m0-cs1 }tsadctsadc-shutorg }tsadc-pin }uart0uart0-xfer }&uart1uart1m0-xfer }  uart1m0-ctsn }uart1m0-rtsn } uart2uart2m0-xfer }uart3uart3m0-xfer }uart4uart4m0-xfer }uart5uart5m0-xfer }uart6uart6m0-xfer }uart7uart7m0-xfer }uart8uart8m0-xfer }uart9uart9m0-xfer }vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2bluetoothbt-reg-on-h }bt-wake-host-h }host-wake-bt-h }ledswork-led }pciepcie20-pins0 } _pcie20-pwren }usbusb-host-pwren-h }usb-otg-pwren-h }wifiwifi-reg-on-h }wifi-wake-host-h }opp-table-0,operating-points-v2 opp-408000000 Q P P0 @opp-600000000 #F P P0 @opp-816000000 0, P P0 @ opp-1104000000 Aʹ 0 @opp-1416000000 Tfr 0 @opp-1608000000 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio6-supplyvccio7-supplyvccio5-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplyphy-handlereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr104spi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthcap-mmc-highspeedmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathcolordefault-statefunctionlinux,default-triggerenable-active-highpost-power-on-delay-mspower-off-delay-us