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spdif@01c21000:2allwinner,sun6i-a31-spdif W>c+ apbspdifKPrxtx ^disabledlradc@01c228002allwinner,sun4i-a10-lradc-keys( ^okayZbutton@158 fVolume Uplswl button@349 fVolume DownlrwTrtp@01c250002allwinner,sun6i-a31-tsP OUserial@01c280002snps,dw-apb-uart€ WG3KPrxtx ^disabledserial@01c284002snps,dw-apb-uart„ WH4KPrxtx ^disabledserial@01c288002snps,dw-apb-uartˆ WI5KPrxtx ^disabledserial@01c28c002snps,dw-apb-uartŒ WJ6K  Prxtx ^disabledserial@01c290002snps,dw-apb-uart WK7K  Prxtx ^disabledserial@01c294002snps,dw-apb-uart” WL8KPrxtx ^disabledi2c@01c2ac002allwinner,sun6i-a31-i2c¬ WC/^failed*default8i2c@01c2b0002allwinner,sun6i-a31-i2c° WD0^okay*default8ctp@5d*default8 2goodix,gt911] i2c@01c2b4002allwinner,sun6i-a31-i2c´ WE1^okay*default8accelerometer@1c*default8 2fsl,mma8452 i2c@01c2b8002allwinner,sun6i-a31-i2c¸ WF2 ^disabledethernet@01c300002allwinner,sun7i-a20-gmacT Rmmacirq W!stmmacethallwinner_gmac_tx  stmmaceth ^disabledcrypto-engine@01c150002allwinner,sun4i-a10-cryptoP PW\ahbmodahbcodec@01c22c00:2allwinner,sun6i-a31-codec, W= apbcodec*KPrxtx ^disabledtimer@01c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer03456W#spi@01c680002allwinner,sun6i-a31-spiƀ AW$]ahbmodKPrxtx ^disabledspi@01c690002allwinner,sun6i-a31-spiƐ BW%^ahbmodKPrxtx ^disabledspi@01c6a0002allwinner,sun6i-a31-spiƠ CW&_ahbmodKPrxtx ^disabledspi@01c6b0002allwinner,sun6i-a31-spiư DW'`ahbmodKPrxtx ^disabledinterrupt-controller@01c81000%2arm,cortex-a7-gicarm,cortex-a15-gic  @ `   OUdisplay-frontend@01e00000%2allwinner,sun6i-a31-display-frontend ]W5|u ahbmodram!O U portsport@1endpoint@0OUdisplay-backend@01e60000$2allwinner,sun6i-a31-display-backend _W3zw ahbmodramzportsport@0endpoint@0OUport@1endpoint@0O U drc@01e700002allwinner,sun6i-a31-drc [W;q ahbmodram'portsport@0endpoint@0 OUport@1endpoint@0!O U rtc@01f000002allwinner,sun6i-a31-rtcT()interrupt-controller@01f00c0c2allwinner,sun6i-a31-sc-nmi 8 O)U)prcm@01f014002allwinner,sun6i-a31-prcmar100_clk2allwinner,sun6i-a31-ar100-clkW  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#address-cells#size-cellsinterrupt-parentmodelcompatiblerangesallwinner,pipelineclocksstatusvcc-lcd-supplyvdd-mipi-bridge-supplyethernet0device_typereginterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-methodclock-latencyoperating-points#cooling-cellscooling-min-levelcooling-max-levelcpu-supplylinux,phandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresis#clock-cellsclock-output-namesallwinner,pipelinesresets#dma-cellsreset-namesclock-namesremote-endpointpinctrl-namespinctrl-0vmmc-supplybus-widthcd-gpioscd-invertedinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cellsusb1_vbus-supply#reset-cellsgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cellsdmasdma-namesvref-supplylabellinux,codechannelvoltage#thermal-sensor-cellsreg-shiftreg-io-widthtouchscreen-swapped-x-y#io-channel-cellssnps,pblsnps,fixed-burstsnps,force_sf_dma_modeassigned-clocksassigned-clock-ratesclock-divclock-multx-powers,dcdc-freqregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltregulator-boot-onenable-active-highgpio