8( $Hgoogle,veyron-minnie-rev4google,veyron-minnie-rev3google,veyron-minnie-rev2google,veyron-minnie-rev1google,veyron-minnie-rev0google,veyron-minniegoogle,veyronrockchip,rk3288&7Google Minniealiases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12h w@\@p@ @@OOa sB@ ~ ' 9 K 0 *@8?KQcpu@501cpuarm,cortex-a12KQcpu@502cpuarm,cortex-a12KQcpu@503cpuarm,cortex-a12KQamba simple-busYdma-controller@ff250000arm,pl330arm,primecell%@`k8 apb_pclkKQdma-controller@ff600000arm,pl330arm,primecell`@`k8 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@`k8 apb_pclkKeQereserved-memoryYdma-unusable@fe000000oscillator fixed-clockn6xin24mK Q timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 8 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 8Drvbiuciuciu-driveciu-sample  @okay (9 K TZr| defaultdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 8Eswbiuciuciu-driveciu-sample ! @okay (rdefault |dwmmc@ff0e0000rockchip,rk3288-dw-mshcр 8Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 8Guybiuciuciu-driveciu-sample #@okay Trdefault saradc@ff100000rockchip,saradc $)8I[saradcapb_pclkW ;saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi8ARspiclkapb_pclkG  Ltxrx ,default !"okayec@0google,cros-ec-spiV& default#s-i2c-tunnelgoogle,cros-ec-i2c-tunnelbq27500@55 ti,bq27500Ukeyboard-controllergoogle,cros-ec-keyb @};0DY1 d>"A#( C  \=@V B |)<?   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi8BSspiclkapb_pclkG Ltxrx -default$%&' disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi8CTspiclkapb_pclkGLtxrx .default()*+okay flash@0jedec,spi-norsi2c@ff140000rockchip,rk3288-i2c >i2c8Mdefault,okay2 dtpm@20infineon,slb9645tt #i2c@ff150000rockchip,rk3288-i2c ?i2c8Odefault-okay2 ,touchscreen@10elan,ekth3500&.default/0 ;.G1T1i2c@ff160000rockchip,rk3288-i2c @i2c8Pdefault2okay2 ,ts3a227e@3b ti,ts3a227e;&3default4aKQtrackpad@15elan,ekth3000& default5l6wi2c@ff170000rockchip,rk3288-i2c Ai2c8Qdefault7okay, KxQxserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 78MUbaudclkapb_pclkdefault 89:okayMlserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 88NVbaudclkapb_pclkdefault;okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 98OWbaudclkapb_pclkdefault<okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :8PXbaudclkapb_pclkdefault= disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;8QYbaudclkapb_pclkdefault> disabledthermal-zonesreserve_thermal?cpu_thermald?tripscpu_alert0ppassiveK@Q@cpu_alert1$passiveKAQAcpu_crit_ criticalcooling-mapsmap0 @ map1 A gpu_thermald?tripsgpu_alert0ppassiveKBQBgpu_crit_ criticalcooling-mapsmap0 B tsadc@ff280000rockchip,rk3288-tsadc( %8HZtsadcapb_pclk ;tsadc-apbinitdefaultsleepC D*C4JsokayaxK?Q?ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqE88fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB ;stmmaceth disabledusb@ff500000 generic-ehciP 8usbhostFusbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 8otghostG usb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 8otghost@@ H usb2-phyokayz Husb@ff5c0000 generic-ehci\ 8usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c8LdefaultIokay2 dpmic@1brockchip,rk808xin32kwifibt_32kin&3default JKL$wEQ]iuM6MMKQregulatorsDCDC_REG1vdd_arm q& >qKQregulator-state-memSDCDC_REG2vdd_gpu 5&>qregulator-state-memlB@DCDC_REG3 vcc135_ddrregulator-state-memlDCDC_REG4vcc_18w@&w@KQregulator-state-memlw@LDO_REG1 vcc33_io2Z&2ZK6Q6regulator-state-meml2ZLDO_REG3vdd_10B@&B@regulator-state-memlB@LDO_REG7vdd10_lcd_pwren_h&%&&%regulator-state-memSSWITCH_REG1 vcc33_lcdKcQcregulator-state-memSLDO_REG6 vcc18_codecw@&w@KdQdregulator-state-memSLDO_REG4 vccio_sdw@&2ZKQregulator-state-memSLDO_REG5 vcc33_sd2Z&2ZK Q regulator-state-memSLDO_REG8 vcc33_ccd2Z&2Zregulator-state-meml2ZLDO_REG22Z&2Z vcc33_touchK1Q1regulator-state-memSSWITCH_REG2 vcc5v_touchregulator-state-memSi2c@ff660000rockchip,rk3288-i2cf =i2c8NdefaultNokay2  max98090@10maxim,max98090&Omclk8qdefaultPKQpwm@ff680000rockchip,rk3288-pwmhdefaultQ8^pwmokayKQpwm@ff680010rockchip,rk3288-pwmhdefaultR8^pwmokaypwm@ff680020rockchip,rk3288-pwmh defaultS8^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0defaultT8^pwm disabledbus_intmem@ff700000 mmio-sramp Ypsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsKQpower-controller!rockchip,rk3288-power-controllerh KhQhpd_vio@9 8chgfdehilkj$UVWXYZ[\]pd_hevc@11 8op^_pd_video@12 8`pd_gpu@13 8abreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruvEHjk$#gׄeрxhрxhKQsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwKEQEedp-phyrockchip,rk3288-dp-phy8h24mokayKsQsio-domains"rockchip,rk3288-io-voltage-domainokay6%0>6N6\chtdusbphyrockchip,rk3288-usb-phyokayusb-phy@320 8]phyclkKHQHusb-phy@33448^phyclkKFQFusb-phy@348H8_phyclkKGQGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt8p Ookaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif hclkmclk8TGeLtx 6defaultfE disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5GeeLtxrxi2s_hclki2s_clk8RdefaultgokayKQcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 8}aclkhclksclkapb_pclk ;crypto-rstokayvop@ff930000rockchip,rk3288-vop 8aclk_vopdclk_vophclk_voph def ;axiahbdclkiokayportK Q endpoint@0jKyQyendpoint@1kKuQuendpoint@2lKqQqiommu@ff930300rockchip,iommu  vopb_mmuh okayKiQivop@ff940000rockchip,rk3288-vop 8aclk_vopdclk_vophclk_voph  ;axiahbdclkmokayportK Q endpoint@0nKzQzendpoint@1oKvQvendpoint@2pKrQriommu@ff940300rockchip,iommu  vopl_mmuh okayKmQmmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 8~d refpclkh E disabledportsportendpoint@0qKlQlendpoint@1rKpQpdp@ff970000rockchip,rk3288-dp@ b8icdppclksdpo;dpEokaydefaulttportsport@0endpoint@0uKkQkendpoint@1vKoQoport@1endpointwKQhdmi@ff980000rockchip,rk3288-dw-hdmiE g8hm iahbisfrh okay xportsportendpoint@0yKjQjendpoint@1zKnQnqos@ffaa0000syscon KaQaqos@ffaa0080syscon KbQbqos@ffad0000syscon KVQVqos@ffad0100syscon KWQWqos@ffad0180syscon KXQXqos@ffad0400syscon KYQYqos@ffad0480syscon KZQZqos@ffad0500syscon KUQUqos@ffad0800syscon K[Q[qos@ffad0880syscon K\Q\qos@ffad0900syscon K]Q]qos@ffae0000syscon K`Q`qos@ffaf0000syscon K^Q^qos@ffaf0080syscon K_Q_interrupt-controller@ffc01000 arm,gic-400  (  @ `   KQefuse@ffb40000rockchip,rk3288-efuse 8q pclk_efusecpu_leakage@17pinctrlrockchip,rk3288-pinctrlEYdefaultsleep{| {}gpio0@ff750000rockchip,gpio-banku Q8@ 9 I  (K3Q3gpio1@ff780000rockchip,gpio-bankx R8A 9 I  (gpio2@ff790000rockchip,gpio-banky S8B 9 I  (K.Q.gpio3@ff7a0000rockchip,gpio-bankz T8C 9 I  (gpio4@ff7b0000rockchip,gpio-bank{ U8D 9 I  (KQgpio5@ff7c0000rockchip,gpio-bank| V8E 9 I  (KQgpio6@ff7d0000rockchip,gpio-bank} W8F 9 I  (KOQOgpio7@ff7e0000rockchip,gpio-bank~ X8G 9 I  (K Q gpio8@ff7f0000rockchip,gpio-bank Y8H 9 I  (hdmihdmi-ddc U~~vcc50-hdmi-en U~KQpcfg-pull-up cKQpcfg-pull-down pKQpcfg-pull-none K~Q~pcfg-pull-none-12ma  KQsleepglobal-pwroff U~K{Q{ddrio-pwroff U~ddr0-retention Uddr1-retention Uedpedp-hpd U KtQti2c0i2c0-xfer U~~KIQIi2c1i2c1-xfer U~~K,Q,i2c2i2c2-xfer U ~ ~KNQNi2c3i2c3-xfer U~~K-Q-i2c4i2c4-xfer U~~K2Q2i2c5i2c5-xfer U~~K7Q7i2s0i2s0-bus` U~~~~~~KgQgsdmmcsdmmc-clk UKQsdmmc-cmd UKQsdmmc-cd Usdmmc-bus1 Usdmmc-bus4@ UKQsdmmc-cd-disabled U~KQsdmmc-cd-gpio U~KQsdio0sdio0-bus1 Usdio0-bus4@ UKQsdio0-cmd UKQsdio0-clk UKQsdio0-cd Usdio0-wp Usdio0-pwr Usdio0-bkpwr Usdio0-int Uwifienable-h U~KQbt-enable-l U~KQsdio1sdio1-bus1 Usdio1-bus4@ Usdio1-cd Usdio1-wp Usdio1-bkpwr Usdio1-int Usdio1-cmd Usdio1-clk U~sdio1-pwr U emmcemmc-clk UKQemmc-cmd UKQemmc-pwr U emmc-bus1 Uemmc-bus4@ Uemmc-bus8 UKQemmc-reset U ~KQspi0spi0-clk U KQspi0-cs0 U K"Q"spi0-tx UK Q spi0-rx UK!Q!spi0-cs1 Uspi1spi1-clk U K$Q$spi1-cs0 U K'Q'spi1-rx UK&Q&spi1-tx UK%Q%spi2spi2-cs1 Uspi2-clk UK(Q(spi2-cs0 UK+Q+spi2-rx UK*Q*spi2-tx U K)Q)uart0uart0-xfer U~K8Q8uart0-cts UK9Q9uart0-rts U~K:Q:uart1uart1-xfer U ~K;Q;uart1-cts U uart1-rts U ~uart2uart2-xfer U~K<Q<uart3uart3-xfer U~K=Q=uart3-cts U uart3-rts U ~uart4uart4-xfer U  ~K>Q>uart4-cts Uuart4-rts U~tsadcotp-gpio U ~KCQCotp-out U ~KDQDpwm0pwm0-pin U~KQQQpwm1pwm1-pin U~KRQRpwm2pwm2-pin U~KSQSpwm3pwm3-pin U~KTQTgmacrgmii-pins U~~~~~~~ ~~rmii-pins U~~~~~~~~~~spdifspdif-tx U ~KfQfpcfg-pull-none-drv-8ma  KQpcfg-pull-up-drv-8ma c pcfg-output-high KQpcfg-output-low KQbuttonspwr-key-l UKQap-lid-int-l UKQvolum-down-l U KQvolum-up-l U KQpmicpmic-int-l UKJQJdvs-1 U KKQKdvs-2 UKLQLrebootap-warm-reset-h U ~KQrecovery-switchrec-mode-l U tpmtpm-int-h U~write-protectfw-wp-ap U~codechp-det UKQint-codec UKPQPmic-det U KQheadsetts3a227e-int-l UK4Q4backlightbl-en U~KQbl_pwr_en U ~KQchargerac-present-ap UKQcros-ecec-int U~K#Q#suspendsuspend-l-wake UK|Q|suspend-l-sleep UK}Q}trackpadtrackpad-int UK5Q5usb-hosthost1-pwr-en U ~KQusbotg-pwren-h U ~KQbuck-5vdrv-5v U~KQlcdlcd-en U~KQavdd-1v8-disp-en U ~KQprochotgpio-prochot U~touchscreentouch-int U~K/Q/touch-rst U~K0Q0memory@0memorygpio-keys gpio-keysdefaultpower Power N3 t dwlid Lid N3w   volum_down Volum_down N  r dvolum_up Volum_up N  s dgpio-restart gpio-restart N3 default emmc-pwrseqmmc-pwrseq-emmcdefault ;. KQsdio-pwrseqmmc-pwrseq-simple8 ext_clockdefault ;KQvcc-5vregulator-fixedvcc_5vLK@&LK@   defaultKMQMvcc33-sysregulator-fixed vcc33_sys2Z&2Z KQvcc50-hdmiregulator-fixed vcc50_hdmi M  defaultsound!rockchip,rockchip-audio-max98090default VEYRON-I2S ! 9 NO dO  {backlightpwm-backlight   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~   default B@ ' KQgpio-charger gpio-charger mains N3defaultpanelauo,b101ean01simple-panelokay  portsportendpointKwQwvccsysregulator-fixedvccsysKQvcc5-host1-regulatorregulator-fixed  3 default vcc5_host1vcc5v-otg-regulatorregulator-fixed  3 default vcc5_host2backlight-regulatorregulator-fixed  . defaultbacklight_regulator  :KQpanel-regulatorregulator-fixed  defaultpanel_regulator  KQvcc18-lcdregulator-fixed  . default vcc18_lcd  #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsmax-frequencyfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasenum-slotssd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removable#io-channel-cellsreset-namesdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-buskeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreset-gpiosvcc33-supplyvccio-supplyti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-widthassigned-clocksassigned-clock-ratespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphysphy-namesneeds-reset-on-resumedr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cells#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowlabellinux,codedebounce-intervallinux,input-typepriorityvin-supplyenable-active-highgpiorockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecbrightness-levelsdefault-brightness-levelenable-gpiosbacklight-boot-offpwmspwm-delay-uspower-supplycharger-typebacklightstartup-delay-us