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#address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyfifo-depthmax-frequencybus-widthdisable-wpnum-slotsvmmc-supplycap-mmc-highspeedcap-sd-highspeednon-removablevqmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loadervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#reset-cellsassigned-clocksassigned-clock-rates#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highgpioswakeup-sourcelabellinux,codepwmsvoltage-tablevin-supplyenable-active-highgpiostartup-delay-us