Ð þíQÕ8L°(%Lx',mundoreader,bq-curie2rockchip,rk3066a 7bq Curie 2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/dwmmc@1021c000f/dwmmc@10214000l/dwmmc@10218000r/serial@10124000z/serial@10126000‚/serial@20064000Š/serial@20068000’/spi@20070000—/spi@20074000amba ,simple-busœdma-controller@20018000,arm,pl330arm,primecell£ €@§²½ØÀ ßapb_pclkëñdma-controller@2001c000,arm,pl330arm,primecell£ À@§²½ØÀ ßapb_pclk ùdisableddma-controller@20078000,arm,pl330arm,primecell£ €@§²½ØÁ ßapb_pclkë ñ oscillator ,fixed-clockn6xin24ml2-cache-controller@10138000,arm,pl310-cache£€0>ë'ñ'scu@1013c000,arm,cortex-a9-scu£Àglobal-timer@1013c200,arm,cortex-a9-global-timer£  § Ølocal-timer@1013c600,arm,cortex-a9-twd-timer£Æ  § Øinterrupt-controller@1013d000,arm,cortex-a9-gicJ_£ÐÁëñserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart£@ §"pzßbaudclkapb_pclkØ@Lùokay‡Œtxrx–default¤serial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart£` §#pzßbaudclkapb_pclkØAMùokay‡Œtxrx–default¤usb@10180000,rockchip,rk3066-usbsnps,dwc2£ §ØÃßotg®otg¶È×€€@@ æ ëusb2-phy ùdisabledusb@101c0000 ,snps,dwc2£ §ØÉßotg®hostæ ëusb2-phy ùdisabledethernet@10204000,rockchip,rk3066-emac£ @< §õØÄD ßhclkmacrefd rmii ùdisableddwmmc@10214000,rockchip,rk2928-dw-mshc£!@ §ØÀHßbiuciuùokayúð€‡ Œrx-tx úð€–default¤ .8DN`qdwmmc@10218000,rockchip,rk2928-dw-mshc£!€ §ØÁIßbiuciuùokay‡ Œrx-tx–default ¤.|Dqdwmmc@1021c000,rockchip,rk2928-dw-mshc£!À §ØÂJßbiuciu ùdisabled‡ Œrx-txpmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd£ @reboot-mode,syscon-reboot-modeŠ@‘RBÃRBëRBà »RBÃgrf@20008000,syscon£ €ëñi2c@2002d000,rockchip,rk3066-i2c£ Ð §(õßi2cØP ùdisabled–default¤i2c@2002f000,rockchip,rk3066-i2c£ ð §)õØQßi2cùokay–default¤€tps@2d£-§ÇÓ ,ti,tps65910regulatorsregulator@0ßvcc_rtcî£vrtcregulator@1ßvcc_ioî£vioëñregulator@2ßvdd_arm 'À/ã`Gî£vdd1ë(ñ(regulator@3ßvcc_ddr 'À/ã`Gî£vdd2regulator@5 ßvcc18_cifî£vdig1regulator@6ßvdd_11î£vdig2regulator@7ßvcc_25î£vpllregulator@8ßvcc_18î£vdacregulator@9 ßvcc25_hdmiî£ vaux1regulator@10ßvcca_33î£ vaux2regulator@11ßvcc_tpî£ vaux33regulator@12 ßvcc28_cifî£ vmmcregulator@4£vdd3regulator@13£ vbbpwm@20030000,rockchip,rk2928-pwm£ YØF ùdisabled–default¤pwm@20030010,rockchip,rk2928-pwm£ YØF ùdisabled–default¤watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt£ ÀØK §3ùokaypwm@20050020,rockchip,rk2928-pwm£  YØG ùdisabled–default¤pwm@20050030,rockchip,rk2928-pwm£ 0YØGùokay–default¤ë.ñ.i2c@20056000,rockchip,rk3066-i2c£ ` §*õØRßi2c ùdisabled–default¤i2c@2005a000,rockchip,rk3066-i2c£   §+õØSßi2c ùdisabled–default¤i2c@2005e000,rockchip,rk3066-i2c£ à §4õØTßi2c ùdisabled–default¤serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart£ @ §$pzßbaudclkapb_pclkØBNùokay‡  Œtxrx–default¤serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart£ € §%pzßbaudclkapb_pclkØCOùokay‡  Œtxrx–default¤saradc@2006c000,rockchip,saradc£ À §dØGJßsaradcapb_pclkvW }saradc-apb ùdisabledspi@20070000,rockchip,rk3066-spiØEHßspiclkapb_pclk §&£ ‡ Œtxrx ùdisabled–default¤ !"spi@20074000,rockchip,rk3066-spiØFIßspiclkapb_pclk §'£ @‡ Œtxrx ùdisabled–default¤#$%&cpus‰rockchip,rk3066-smpcpu@0—cpu,arm,cortex-a9£'£8´›@Ö O€íØa€*ˆ s€*ˆ 'ÀÈà°ÀÈàÂÀg8Åœ@ØÓ(cpu@1—cpu,arm,cortex-a9£'£sram@10080000 ,mmio-sram£ œsmp-sram@0,rockchip,rk3066-smp-sram£Pi2s@10118000,rockchip,rk3066-i2s£€  §–default¤)‡Œtxrxßi2s_hclki2s_clkØÆKßú ùdisabledi2s@1011a000,rockchip,rk3066-i2s£   § –default¤*‡Œtxrxßi2s_hclki2s_clkØÇLßú ùdisabledi2s@1011c000,rockchip,rk3066-i2s£À  §–default¤+‡  Œtxrxßi2s_hclki2s_clkØÈMßú ùdisabledclock-controller@20000000,rockchip,rk3066a-cru£ õ@!ËÔ^ÌÕ_ 1ׄ#g¸€á£ðÑ€xhÀá£ðÑ€xhÀëñtimer@2000e000,snps,dw-apb-timer-osc£ à §.ØVD ßtimerpclkefuse@20010000,rockchip,rk3066a-efuse£ @Ø[ ßpclk_efusecpu_leakage@17£timer@20038000,snps,dw-apb-timer-osc£ € §,ØTB ßtimerpclktimer@2003a000,snps,dw-apb-timer-osc£   §-ØUC ßtimerpclktsadc@20060000,rockchip,rk3066-tsadc£ Ø]]ßsaradcapb_pclk §dv\ }saradc-apb ùdisabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyõ ùdisabledusb-phy@17cF£|ØQßphyclkëñusb-phy@188F£ˆØRßphyclkëñpinctrl,rockchip,rk3066a-pinctrlõœgpio0@20034000,rockchip,gpio-bank£ @ §6ØUQaJ_gpio1@2003c000,rockchip,gpio-bank£ À §7ØVQaJ_gpio2@2003e000,rockchip,gpio-bank£ à §8ØWQaJ_gpio3@20080000,rockchip,gpio-bank£  §9ØXQaJ_ë/ñ/gpio4@20084000,rockchip,gpio-bank£ @ §:ØYQaJ_ë0ñ0gpio6@2000a000,rockchip,gpio-bank£   §<ØZQaJ_ëñpcfg_pull_defaultmë-ñ-pcfg_pull_noneƒë,ñ,emacemac-xfer€,,,,,,,,emac-mdio ,,emmcemmc-clk-emmc-cmd -emmc-rst -i2c0i2c0-xfer ,,ëñi2c1i2c1-xfer ,,ëñi2c2i2c2-xfer ,,ëñi2c3i2c3-xfer ,,ëñi2c4i2c4-xfer ,,ëñpwm0pwm0-out,ëñpwm1pwm1-out,ëñpwm2pwm2-out,ëñpwm3pwm3-out,ëñspi0spi0-clk-ëñspi0-cs0-ë"ñ"spi0-tx-ë ñ spi0-rx-ë!ñ!spi0-cs1-spi1spi1-clk-ë#ñ#spi1-cs0-ë&ñ&spi1-rx-ë%ñ%spi1-tx-ë$ñ$spi1-cs1-uart0uart0-xfer --ëñuart0-cts-uart0-rts-uart1uart1-xfer --ëñuart1-cts-uart1-rts-uart2uart2-xfer - -ëñuart3uart3-xfer --ëñuart3-cts-uart3-rts-sd0sd0-clk-ë ñ sd0-cmd -ë ñ sd0-cd-ë ñ sd0-wp-sd0-bus-width1 -sd0-bus-width4@ - - - -ë ñ sd1sd1-clk-ëñsd1-cmd-ëñsd1-cd-sd1-wp-sd1-bus-width1-sd1-bus-width4@----ëñi2s0i2s0-bus-- - - - - ---ë)ñ)i2s1i2s1-bus`------ë*ñ*i2s2i2s2-bus`------ë+ñ+memory@60000000—memory£`@vdd-log,pwm-regulator ž.èßvdd_logO€/O€î£B@dO€*ùokayfixed-regulator,regulator-fixed ßsdmmc-supply-ÆÀ/-ÆÀ ±/¶† Çëñgpio-keys ,gpio-keysÒpower ÝãtîGPIO Key Powerôdvolume-down Ý0ãrîGPIO Key Vol-ôd #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushpclocksclock-nameslinux,phandlestatusclock-frequency#clock-cellsclock-output-namescache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modefifo-depthmax-frequencynum-slotsvmmc-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpnon-removableoffsetmode-normalmode-recoverymode-bootloadermode-loadervcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsresetsreset-namesenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu0-supplyrockchip,playback-channelsrockchip,capture-channels#reset-cellsassigned-clocksassigned-clock-rates#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinspwmsvoltage-tablegpiostartup-delay-usvin-supplyautorepeatgpioslinux,codelabellinux,input-typewakeup-sourcedebounce-interval