Ð þíÅG8¾”(³¾\%motorola,droid4ti,omap4430ti,omap4 +7Motorola Droid 4 XT894chosen=/ocp/serial@48020000aliasesI/ocp/i2c@48070000N/ocp/i2c@48072000S/ocp/i2c@48060000X/ocp/i2c@48350000]/ocp/serial@4806a000e/ocp/serial@4806c000m/ocp/serial@48020000u/ocp/serial@4806e000cpus+cpu@0arm,cortex-a9}cpu‰šž¥cpu±“à ¿“à£è 'ÀO€ 5èa€ûÐâô cpu@1arm,cortex-a9}cpu‰šinterrupt-controller@48241000arm,cortex-a9-gic&šH$H$  l2-cache-controller@48242000arm,pl310-cachešH$ 7E local-timer@48240600arm,cortex-a9-twd-timeržšH$  Q  interrupt-controller@48281000ti,omap4-wugen-mpu&šH(  socti,omap-inframpu ti,omap4-mpu\mpufdsp ti,omap3-c64\dspiva ti,ivahd\ivaocpti,omap4-l3-nocsimple-bus+k\l3_main_1l3_main_2l3_main_3šDD€ EQ  l4@4a000000ti,omap4-l4-cfgsimple-bus+ kJcm1@4000 ti,omap4-cm1š@ clocks+extalt_clkin_ckr fixed-clock„DÀ: :pad_clks_src_ckr fixed-clock· pad_clks_ck@108rti,gate-clockžš& &pad_slimbus_core_clks_ckr fixed-clock·F Fsecure_32k_clk_src_ckr fixed-clock€slimbus_src_clkr fixed-clock· slimbus_clk@108rti,gate-clockž š' 'sys_32k_ckr fixed-clock€, ,virt_12000000_ckr fixed-clock·S Svirt_13000000_ckr fixed-clockÆ]@T Tvirt_16800000_ckr fixed-clockYU Uvirt_19200000_ckr fixed-clock$øV Vvirt_26000000_ckr fixed-clockŒº€W Wvirt_27000000_ckr fixed-clock›üÀX Xvirt_38400000_ckr fixed-clockIðY Ytie_low_clock_ckr fixed-clock] ]utmi_phy_clkout_ckr fixed-clock“‡M Mxclk60mhsp1_ckr fixed-clock“‡I Ixclk60mhsp2_ckr fixed-clock“‡K Kxclk60motg_ckr fixed-clock“‡N Ndpll_abe_ck@1e0rti,omap4-dpll-m4xen-clockž šàäìè  dpll_abe_x2_ck@1f0rti,omap4-dpll-x2-clockž šð  dpll_abe_m2x2_ck@1f0rti,divider-clockž œ§šð¹Ð  abe_24m_fclkrfixed-factor-clockž çò" "abe_clk@108rti,divider-clockž œšü aess_fclk@528rti,divider-clockžœš(  dpll_abe_m3x2_ck@1f4rti,divider-clockž œ§šô¹Ð core_hsd_byp_clk_mux_ck@12cr ti,mux-clockžš, dpll_core_ck@120rti,omap4-dpll-core-clockžš $,( dpll_core_x2_ckrti,omap4-dpll-x2-clockž dpll_core_m6x2_ck@140rti,divider-clockžœ§š@¹Ð\ \dpll_core_m2_ck@130rti,divider-clockžœ§š0¹Ð ddrphy_ckrfixed-factor-clockžçòdpll_core_m5x2_ck@13crti,divider-clockžœ§š<¹Ð div_core_ck@100rti,divider-clockžšœ div_iva_hs_clk@1dcrti,divider-clockžœšÜü div_mpu_hs_clk@19crti,divider-clockžœšœü dpll_core_m4x2_ck@138rti,divider-clockžœ§š8¹Ð dll_clk_div_ckrfixed-factor-clockžçòdpll_abe_m2_ck@1f0rti,divider-clockž œšð¹! !dpll_core_m3x2_gate_ck@134r ti,composite-no-wait-gate-clockžš4 dpll_core_m3x2_div_ck@134rti,composite-divider-clockžœš4¹ dpll_core_m3x2_ckrti,composite-clockžb bdpll_core_m7x2_ck@144rti,divider-clockžœ§šD¹Ð= =iva_hsd_byp_clk_mux_ck@1acr ti,mux-clockžš¬ dpll_iva_ck@1a0rti,omap4-dpll-clockžš ¤¬¨ dpll_iva_x2_ckrti,omap4-dpll-x2-clockž dpll_iva_m4x2_ck@1b8rti,divider-clockžœ§š¸¹Ðdpll_iva_m5x2_ck@1bcrti,divider-clockžœ§š¼¹Ðdpll_mpu_ck@160rti,omap4-dpll-clockžš`dlh dpll_mpu_m2_ck@170rti,divider-clockžœ§šp¹Ðper_hs_clk_div_ckrfixed-factor-clockžçò- -usb_hs_clk_div_ckrfixed-factor-clockžçò3 3l3_div_ck@100rti,divider-clockžœš l4_div_ck@100rti,divider-clockžœšP Plp_clk_div_ckrfixed-factor-clockž çòZ Zmpu_periphclkrfixed-factor-clockžçò ocp_abe_iclk@528rti,divider-clockž š(per_abe_24m_fclkrfixed-factor-clockž!çòD Ddmic_sync_mux_ck@538r ti,mux-clock ž"#$š8% %func_dmic_abe_gfclk@538r ti,mux-clock ž%&'š8mcasp_sync_mux_ck@540r ti,mux-clock ž"#$š@( (func_mcasp_abe_gfclk@540r ti,mux-clock ž(&'š@mcbsp1_sync_mux_ck@548r ti,mux-clock ž"#$šH) )func_mcbsp1_gfclk@548r ti,mux-clock ž)&'šHmcbsp2_sync_mux_ck@550r ti,mux-clock ž"#$šP* *func_mcbsp2_gfclk@550r ti,mux-clock ž*&'šPmcbsp3_sync_mux_ck@558r ti,mux-clock ž"#$šX+ +func_mcbsp3_gfclk@558r ti,mux-clock ž+&'šXslimbus1_fclk_1@560rti,gate-clockž$ š`slimbus1_fclk_0@560rti,gate-clockž"š`slimbus1_fclk_2@560rti,gate-clockž& š`slimbus1_slimbus_clk@560rti,gate-clockž' š`timer5_sync_mux@568r ti,mux-clockž#,šhtimer6_sync_mux@570r ti,mux-clockž#,šptimer7_sync_mux@578r ti,mux-clockž#,šxtimer8_sync_mux@580r ti,mux-clockž#,š€dummy_ckr fixed-clockclockdomainscm2@8000 ti,omap4-cm2š€0clocks+per_hsd_byp_clk_mux_ck@14cr ti,mux-clockž-šL. .dpll_per_ck@140rti,omap4-dpll-clockž.š@DLH/ /dpll_per_m2_ck@150rti,divider-clockž/œšP¹7 7dpll_per_x2_ck@150rti,omap4-dpll-x2-clockž/šP0 0dpll_per_m2x2_ck@150rti,divider-clockž0œ§šP¹Ð6 6dpll_per_m3x2_gate_ck@154r ti,composite-no-wait-gate-clockž0šT1 1dpll_per_m3x2_div_ck@154rti,composite-divider-clockž0œšT¹2 2dpll_per_m3x2_ckrti,composite-clockž12c cdpll_per_m4x2_ck@158rti,divider-clockž0œ§šX¹Ð8 8dpll_per_m5x2_ck@15crti,divider-clockž0œ§š\¹Ð; ;dpll_per_m6x2_ck@160rti,divider-clockž0œ§š`¹Ð5 5dpll_per_m7x2_ck@164rti,divider-clockž0œ§šd¹Ð> >dpll_usb_ck@180rti,omap4-dpll-j-type-clockž3š€„Œˆ4 4dpll_usb_clkdcoldo_ck@1b4rti,fixed-factor-clockž4§š´+Ðdpll_usb_m2_ck@190rti,divider-clockž4œ§š¹Ð9 9ducati_clk_mux_ck@100r ti,mux-clockž5šfunc_12m_fclkrfixed-factor-clockž6çòfunc_24m_clkrfixed-factor-clockž7çò$ $func_24mc_fclkrfixed-factor-clockž6çòE Efunc_48m_fclk@108rti,divider-clockž6šC Cfunc_48mc_fclkrfixed-factor-clockž6çò< <func_64m_fclk@108rti,divider-clockž8šB Bfunc_96m_fclk@108rti,divider-clockž6š? ?init_60m_fclk@104rti,divider-clockž9šH Hper_abe_nc_fclk@108rti,divider-clockž!šœ@ @aes1_fck@15a0rti,gate-clockžš aes2_fck@15a8rti,gate-clockžš¨dss_sys_clk@1120rti,gate-clockž# š ‰ ‰dss_tv_clk@1120rti,gate-clockž: š ˆ ˆdss_dss_clk@1120rti,gate-clockž;š 9‡ ‡dss_48mhz_clk@1120rti,gate-clockž< š Š Šfdif_fck@1028rti,divider-clockž8œš(ügpio2_dbclk@1460rti,gate-clockž,š`gpio3_dbclk@1468rti,gate-clockž,šhgpio4_dbclk@1470rti,gate-clockž,špgpio5_dbclk@1478rti,gate-clockž,šxgpio6_dbclk@1480rti,gate-clockž,š€sgx_clk_mux@1220r ti,mux-clockž=>š hsi_fck@1338rti,divider-clockž6œš8üiss_ctrlclk@1020rti,gate-clockž?š mcbsp4_sync_mux_ck@14e0r ti,mux-clockž?@šàA Aper_mcbsp4_gfclk@14e0r ti,mux-clockžA&šàhsmmc1_fclk@1328r ti,mux-clockžB?š(hsmmc2_fclk@1330r ti,mux-clockžB?š0ocp2scp_usb_phy_phy_48m@13e0rti,gate-clockžCšàsha2md5_fck@15c8rti,gate-clockžšÈslimbus2_fclk_1@1538rti,gate-clockžD š8slimbus2_fclk_0@1538rti,gate-clockžEš8slimbus2_slimbus_clk@1538rti,gate-clockžF š8smartreflex_core_fck@638rti,gate-clockžGš8smartreflex_iva_fck@630rti,gate-clockžGš0smartreflex_mpu_fck@628rti,gate-clockžGš(cm2_dm10_mux@1428r ti,mux-clockž,š(cm2_dm11_mux@1430r ti,mux-clockž,š0cm2_dm2_mux@1438r ti,mux-clockž,š8cm2_dm3_mux@1440r ti,mux-clockž,š@cm2_dm4_mux@1448r ti,mux-clockž,šHcm2_dm9_mux@1450r ti,mux-clockž,šPusb_host_fs_fck@13d0rti,gate-clockž<šÐQ Qutmi_p1_gfclk@1358r ti,mux-clockžHIšXJ Jusb_host_hs_utmi_p1_clk@1358rti,gate-clockžJšXutmi_p2_gfclk@1358r ti,mux-clockžHKšXL Lusb_host_hs_utmi_p2_clk@1358rti,gate-clockžL šXusb_host_hs_utmi_p3_clk@1358rti,gate-clockžH šXusb_host_hs_hsic480m_p1_clk@1358rti,gate-clockž9 šXusb_host_hs_hsic60m_p1_clk@1358rti,gate-clockžH šXusb_host_hs_hsic60m_p2_clk@1358rti,gate-clockžH šXusb_host_hs_hsic480m_p2_clk@1358rti,gate-clockž9šXusb_host_hs_func48mclk@1358rti,gate-clockž<šXusb_host_hs_fck@1358rti,gate-clockžHšXotg_60m_gfclk@1360r ti,mux-clockžMNš`O Ousb_otg_hs_xclk@1360rti,gate-clockžOš`usb_otg_hs_ick@1360rti,gate-clockžš`usb_phy_cm_clk32k@640rti,gate-clockž,š@„ „usb_tll_hs_usb_ch2_clk@1368rti,gate-clockžH šhusb_tll_hs_usb_ch0_clk@1368rti,gate-clockžHšhusb_tll_hs_usb_ch1_clk@1368rti,gate-clockžH šhusb_tll_hs_ick@1368rti,gate-clockžPšhclockdomainsl3_init_clkdmti,clockdomainž4Qscm@2000ti,omap4-scm-coresimple-busš + k scm_conf@0sysconš+scm@100000%ti,omap4-scm-padconf-coresimple-bus+ kpinmux@40 ti,omap4-padconfpinctrl-singleš@–+L&[yÿ} }pinmux_usb_gpio_mux_sel1_pins–Hpinmux_usb_ulpi_pinsp–VXrtvxz|~€‚„†ˆpinmux_usb_utmi_pinsp–VXrtvxz|~€‚„†ˆpinmux_uart3_pinsp–VXrtvxz|~€‚„†ˆomap4_padconf_global@5a0sysconsimple-busš p+ k pR Rpbias_regulator@60ti,pbias-omap4ti,pbias-omapš`ªRpbias_mmc_omap4±pbias_mmc_omap4Àw@Ø-ÆÀ~ ~l4@300000ti,omap4-l4-wkupsimple-bus+ k0counter@4000ti,omap-counter32kš@  \counter_32kprm@6000 ti,omap4-prmš`0 Q clocks+sys_clkin_ck@110r ti,mux-clockžSTUVWXYš¹ abe_dpll_bypass_clk_mux_ck@108r ti,mux-clockž,š  abe_dpll_refclk_mux_ck@10cr ti,mux-clockž,š   dbgclk_mux_ckrfixed-factor-clockžçòl4_wkup_clk_mux_ck@108r ti,mux-clockžZšG Gsyc_clk_div_ck@100rti,divider-clockžšœ# #gpio1_dbclk@1838rti,gate-clockž,š8dmt1_clk_mux@1840r ti,mux-clockž,š@usim_ck@1858rti,divider-clockž8šX[ [usim_fclk@1858rti,gate-clockž[šXpmd_stm_clock_mux_ck@1a20r ti,mux-clock ž\]š ^ ^pmd_trace_clk_mux_ck@1a20r ti,mux-clock ž\]š _ _stm_clk_div_ck@1a20rti,divider-clockž^œ@š ütrace_clk_div_div_ck@1a20rti,divider-clockž_š ` `trace_clk_div_ckrti,clkdm-gate-clockž`a abandgap_fclk@1888rti,gate-clockž,šˆclockdomainsemu_sys_clkdmti,clockdomainžascrm@a000ti,omap4-scrmš  clocks+auxclk0_src_gate_ck@310r ti,composite-no-wait-gate-clockžbšd dauxclk0_src_mux_ck@310rti,composite-mux-clock žbcše eauxclk0_src_ckrti,composite-clockždef fauxclk0_ck@310rti,divider-clockžfœšv vauxclk1_src_gate_ck@314r ti,composite-no-wait-gate-clockžbšg gauxclk1_src_mux_ck@314rti,composite-mux-clock žbcšh hauxclk1_src_ckrti,composite-clockžghi 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compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2i2c3serial0serial1serial2serial3device_typenext-level-cacheregclocksclock-namesclock-latencyoperating-pointscooling-min-levelcooling-max-level#cooling-cellslinux,phandleinterrupt-controller#interrupt-cellscache-unifiedcache-levelinterruptsti,hwmodssramranges#clock-cellsclock-frequencyti,bit-shiftti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,index-power-of-twoti,dividersti,clock-divti,clock-multti,set-rate-parent#pinctrl-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltstatus#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsdmasdma-namesgpmc,num-csgpmc,num-waitpinsti,no-idle-on-initinterrupts-extended#hwlock-cellsti,spi-num-csti,dual-voltti,needs-special-resetpbias-supplyvmmc-supplybus-widthcd-gpiosnon-removablecap-power-off-cardref-clock-frequencytcxo-clock-frequency#iommu-cellsti,iommu-bus-err-backreg-namesinterrupt-namesti,buffer-sizephy-typehw-caps-read-idle-ctrlhw-caps-ll-interfacehw-caps-temp-alertctrl-module#phy-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,timer-dspti,timer-pwmusb-phyphysphy-namesmultipointnum-epsram-bitsinterface-typemodepowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_info#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceregulator-always-ongpiostartup-delay-usenable-active-high