-8P(Dcompulab,omap3-sbc-t3517compulab,omap3-cm-t3517ti,am3517ti,omap3 +!7CompuLab SBC-T3517 with CM-T3517chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@4809e000 l/connector u/connectorcpus+cpu@0arm,cortex-a8~cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2iva disableddsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+%BdefaultPpinmux_uart3_pinsZnpntpinmux_mmc1_pins0Zntpinmux_green_led_pinsZntpinmux_dss_dpi_pins_commonZntpinmux_dss_dpi_pins_cm_t35x0Zntpinmux_ads7846_pinsZntpinmux_mcspi1_pins Zntpinmux_i2c1_pinsZntpinmux_mcbsp2_pins Z ntpinmux_hsusb1_phy_reset_pinsZHntpinmux_hsusb2_phy_reset_pinsZJntpinmux_otg_drv_vbusZntpinmux_mmc2_pins0Z(*,.02ntpinmux_wl12xx_core_pinsZFntpinmux_usb_hub_pinsZTntpinmux_smsc2_pinsZntpinmux_tfp410_pinsZntpinmux_i2c3_pinsZntpinmux_sb_t35_audio_ampZntpinmux_mmc1_aux_pinsZDntpinmux_sb_t35_usb_hub_pinsZntscm_conf@270sysconsimple-busp0+ p0ntpbias_regulator@2b0ti,pbias-omap3ti,pbias-omap|pbias_mmc_omap2430pbias_mmc_omap2430w@-ntclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhn t mcbsp5_fckti,composite-clock ntmcbsp1_mux_fck@4ti,composite-mux-clockn t mcbsp1_fckti,composite-clock ntmcbsp2_mux_fck@4ti,composite-mux-clock ntmcbsp2_fckti,composite-clock ntmcbsp3_mux_fck@68ti,composite-mux-clock hntmcbsp3_fckti,composite-clockntmcbsp4_mux_fck@68ti,composite-mux-clock hntmcbsp4_fckti,composite-clockntemac_ick@32cti,am35xx-gate-clock,nztzemac_fck@32cti,gate-clock, vpfe_ick@32cti,am35xx-gate-clock,n{t{vpfe_fck@32cti,gate-clock, hsotgusb_ick_am35xx@32cti,am35xx-gate-clock,n|t|hsotgusb_fck_am35xx@32cti,gate-clock,n}t}hecc_ck@32cti,am35xx-gate-clock,n~t~clockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+%pinmux_wl12xx_wkup_pinsZntaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYntosc_sys_ck@d40 ti,mux-clock @ntsys_ck@1270ti,divider-clockpntsys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clock(dpll3_m2x2_ckfixed-factor-clock (n"t"dpll4_x2_ckfixed-factor-clock!(corex2_fckfixed-factor-clock"(n#t#wkup_l4_ickfixed-factor-clock(nRtRcorex2_d3_fckfixed-factor-clock#(nstscorex2_d5_fckfixed-factor-clock#(ntttclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clocknDtDvirt_12m_ck fixed-clockntvirt_13m_ck fixed-clock]@ntvirt_19200000_ck fixed-clock$ntvirt_26000000_ck fixed-clockntvirt_38_4m_ck fixed-clockIntdpll4_ck@d00ti,omap3-dpll-per-clock D 0n!t!dpll4_m2_ck@d48ti,divider-clock!? Hn$t$dpll4_m2x2_mul_ckfixed-factor-clock$(n%t%dpll4_m2x2_ck@d00ti,gate-clock% 2n&t&omap_96m_alwon_fckfixed-factor-clock&(n-t-dpll3_ck@d00ti,omap3-dpll-core-clock @ 0ntdpll3_m3_ck@1140ti,divider-clock@n't'dpll3_m3x2_mul_ckfixed-factor-clock'(n(t(dpll3_m3x2_ck@d00ti,gate-clock(  2n)t)emu_core_alwon_ckfixed-factor-clock)(nftfsys_altclk fixed-clockn2t2mcbsp_clks fixed-clockntdpll3_m2_ck@d40ti,divider-clock @n t core_ckfixed-factor-clock (n*t*dpll1_fck@940ti,divider-clock* @n+t+dpll1_ck@904ti,omap3-dpll-clock+  $ @ 4ntdpll1_x2_ckfixed-factor-clock(n,t,dpll1_x2m2_ck@944ti,divider-clock, Dn@t@cm_96m_fckfixed-factor-clock-(n.t.omap_96m_fck@d40 ti,mux-clock. @nItIdpll4_m3_ck@e40ti,divider-clock! @n/t/dpll4_m3x2_mul_ckfixed-factor-clock/(n0t0dpll4_m3x2_ck@d00ti,gate-clock0 2n1t1omap_54m_fck@d40 ti,mux-clock12 @n<t<cm_96m_d2_fckfixed-factor-clock.(n3t3omap_48m_fck@d40 ti,mux-clock32 @n4t4omap_12m_fckfixed-factor-clock4(nKtKdpll4_m4_ck@e40ti,divider-clock! @n5t5dpll4_m4x2_mul_ckti,fixed-factor-clock5HVcn6t6dpll4_m4x2_ck@d00ti,gate-clock6 2cnxtxdpll4_m5_ck@f40ti,divider-clock!?@n7t7dpll4_m5x2_mul_ckti,fixed-factor-clock7HVcn8t8dpll4_m5x2_ck@d00ti,gate-clock8 2cdpll4_m6_ck@1140ti,divider-clock!?@n9t9dpll4_m6x2_mul_ckfixed-factor-clock9(n:t:dpll4_m6x2_ck@d00ti,gate-clock: 2n;t;emu_per_alwon_ckfixed-factor-clock;(ngtgclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock* pn=t=clkout2_src_mux_ck@d70ti,composite-mux-clock*.< pn>t>clkout2_src_ckti,composite-clock=>n?t?sys_clkout2@d70ti,divider-clock?@ pvmpu_ckfixed-factor-clock@(nAtAarm_fck@924ti,divider-clockA $emu_mpu_alwon_ckfixed-factor-clockA(nhthl3_ick@a40ti,divider-clock* @nBtBl4_ick@a40ti,divider-clockB @nCtCrm_ick@c40ti,divider-clockC @gpt10_gate_fck@a00ti,composite-gate-clock  nEtEgpt10_mux_fck@a40ti,composite-mux-clockD @nFtFgpt10_fckti,composite-clockEFgpt11_gate_fck@a00ti,composite-gate-clock  nGtGgpt11_mux_fck@a40ti,composite-mux-clockD @nHtHgpt11_fckti,composite-clockGHcore_96m_fckfixed-factor-clockI(ntmmchs2_fck@a00ti,wait-gate-clock ntmmchs1_fck@a00ti,wait-gate-clock nti2c3_fck@a00ti,wait-gate-clock nti2c2_fck@a00ti,wait-gate-clock nti2c1_fck@a00ti,wait-gate-clock ntmcbsp5_gate_fck@a00ti,composite-gate-clock  ntmcbsp1_gate_fck@a00ti,composite-gate-clock  n t core_48m_fckfixed-factor-clock4(nJtJmcspi4_fck@a00ti,wait-gate-clockJ ntmcspi3_fck@a00ti,wait-gate-clockJ ntmcspi2_fck@a00ti,wait-gate-clockJ ntmcspi1_fck@a00ti,wait-gate-clockJ ntuart2_fck@a00ti,wait-gate-clockJ ntuart1_fck@a00ti,wait-gate-clockJ  ntcore_12m_fckfixed-factor-clockK(nLtLhdq_fck@a00ti,wait-gate-clockL ntcore_l3_ickfixed-factor-clockB(nMtMsdrc_ick@a10ti,wait-gate-clockM nytygpmc_fckfixed-factor-clockM(core_l4_ickfixed-factor-clockC(nNtNmmchs2_ick@a10ti,omap3-interface-clockN ntmmchs1_ick@a10ti,omap3-interface-clockN nthdq_ick@a10ti,omap3-interface-clockN ntmcspi4_ick@a10ti,omap3-interface-clockN ntmcspi3_ick@a10ti,omap3-interface-clockN ntmcspi2_ick@a10ti,omap3-interface-clockN ntmcspi1_ick@a10ti,omap3-interface-clockN nti2c3_ick@a10ti,omap3-interface-clockN nti2c2_ick@a10ti,omap3-interface-clockN nti2c1_ick@a10ti,omap3-interface-clockN ntuart2_ick@a10ti,omap3-interface-clockN ntuart1_ick@a10ti,omap3-interface-clockN  ntgpt11_ick@a10ti,omap3-interface-clockN  ntgpt10_ick@a10ti,omap3-interface-clockN  ntmcbsp5_ick@a10ti,omap3-interface-clockN  ntmcbsp1_ick@a10ti,omap3-interface-clockN  ntomapctrl_ick@a10ti,omap3-interface-clockN ntdss_tv_fck@e00ti,gate-clock<ntdss_96m_fck@e00ti,gate-clockIntdss2_alwon_fck@e00ti,gate-clockntdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock nOtOgpt1_mux_fck@c40ti,composite-mux-clockD @nPtPgpt1_fckti,composite-clockOPaes2_ick@a10ti,omap3-interface-clockN ntwkup_32k_fckfixed-factor-clockD(nQtQgpio1_dbck@c00ti,gate-clockQ ntsha12_ick@a10ti,omap3-interface-clockN ntwdt2_fck@c00ti,wait-gate-clockQ ntwdt2_ick@c10ti,omap3-interface-clockR ntwdt1_ick@c10ti,omap3-interface-clockR ntgpio1_ick@c10ti,omap3-interface-clockR ntomap_32ksync_ick@c10ti,omap3-interface-clockR ntgpt12_ick@c10ti,omap3-interface-clockR ntgpt1_ick@c10ti,omap3-interface-clockR ntper_96m_fckfixed-factor-clock-(n t per_48m_fckfixed-factor-clock4(nStSuart3_fck@1000ti,wait-gate-clockS ntgpt2_gate_fck@1000ti,composite-gate-clocknTtTgpt2_mux_fck@1040ti,composite-mux-clockD@nUtUgpt2_fckti,composite-clockTUgpt3_gate_fck@1000ti,composite-gate-clocknVtVgpt3_mux_fck@1040ti,composite-mux-clockD@nWtWgpt3_fckti,composite-clockVWgpt4_gate_fck@1000ti,composite-gate-clocknXtXgpt4_mux_fck@1040ti,composite-mux-clockD@nYtYgpt4_fckti,composite-clockXYgpt5_gate_fck@1000ti,composite-gate-clocknZtZgpt5_mux_fck@1040ti,composite-mux-clockD@n[t[gpt5_fckti,composite-clockZ[gpt6_gate_fck@1000ti,composite-gate-clockn\t\gpt6_mux_fck@1040ti,composite-mux-clockD@n]t]gpt6_fckti,composite-clock\]gpt7_gate_fck@1000ti,composite-gate-clockn^t^gpt7_mux_fck@1040ti,composite-mux-clockD@n_t_gpt7_fckti,composite-clock^_gpt8_gate_fck@1000ti,composite-gate-clock n`t`gpt8_mux_fck@1040ti,composite-mux-clockD@natagpt8_fckti,composite-clock`agpt9_gate_fck@1000ti,composite-gate-clock nbtbgpt9_mux_fck@1040ti,composite-mux-clockD@nctcgpt9_fckti,composite-clockbcper_32k_alwon_fckfixed-factor-clockD(ndtdgpio6_dbck@1000ti,gate-clockdntgpio5_dbck@1000ti,gate-clockdntgpio4_dbck@1000ti,gate-clockdntgpio3_dbck@1000ti,gate-clockdntgpio2_dbck@1000ti,gate-clockd ntwdt3_fck@1000ti,wait-gate-clockd ntper_l4_ickfixed-factor-clockC(netegpio6_ick@1010ti,omap3-interface-clockentgpio5_ick@1010ti,omap3-interface-clockentgpio4_ick@1010ti,omap3-interface-clockentgpio3_ick@1010ti,omap3-interface-clockentgpio2_ick@1010ti,omap3-interface-clocke ntwdt3_ick@1010ti,omap3-interface-clocke ntuart3_ick@1010ti,omap3-interface-clocke ntuart4_ick@1010ti,omap3-interface-clockentgpt9_ick@1010ti,omap3-interface-clocke ntgpt8_ick@1010ti,omap3-interface-clocke ntgpt7_ick@1010ti,omap3-interface-clockentgpt6_ick@1010ti,omap3-interface-clockentgpt5_ick@1010ti,omap3-interface-clockentgpt4_ick@1010ti,omap3-interface-clockentgpt3_ick@1010ti,omap3-interface-clockentgpt2_ick@1010ti,omap3-interface-clockentmcbsp2_ick@1010ti,omap3-interface-clockentmcbsp3_ick@1010ti,omap3-interface-clockentmcbsp4_ick@1010ti,omap3-interface-clockentmcbsp2_gate_fck@1000ti,composite-gate-clockn t mcbsp3_gate_fck@1000ti,composite-gate-clockntmcbsp4_gate_fck@1000ti,composite-gate-clockntemu_src_mux_ck@1140 ti,mux-clockfgh@nitiemu_src_ckti,clkdm-gate-clockinjtjpclk_fck@1140ti,divider-clockj@pclkx2_fck@1140ti,divider-clockj@atclk_fck@1140ti,divider-clockj@traceclk_src_fck@1140 ti,mux-clockfgh@nktktraceclk_fck@1140ti,divider-clockk @secure_32k_fck fixed-clocknltlgpt12_fckfixed-factor-clockl(wdt1_fckfixed-factor-clockl(ipss_ick@a10ti,am35xx-interface-clockM ntrmii_ck fixed-clockntpclk_ck fixed-clockntuart4_ick_am35xx@a10ti,omap3-interface-clockN uart4_fck_am35xx@a00ti,wait-gate-clockJ dpll5_ck@d04ti,omap3-dpll-clock  $ L 4nmtmdpll5_m2_ck@d50ti,divider-clockm Pnwtwsgx_gate_fck@b00ti,composite-gate-clock* nutucore_d3_ckfixed-factor-clock*(nntncore_d4_ckfixed-factor-clock*(notocore_d6_ckfixed-factor-clock*(nptpomap_192m_alwon_fckfixed-factor-clock&(nqtqcore_d2_ckfixed-factor-clock*(nrtrsgx_mux_fck@b40ti,composite-mux-clock nop.qrst @nvtvsgx_fckti,composite-clockuvsgx_ick@b10ti,wait-gate-clockB ntcpefuse_fck@a08ti,gate-clock ntts_fck@a08ti,gate-clockD ntusbtll_fck@a08ti,wait-gate-clockw ntusbtll_ick@a18ti,omap3-interface-clockN ntmmchs3_ick@a10ti,omap3-interface-clockN ntmmchs3_fck@a00ti,wait-gate-clock ntdss1_alwon_fck_3430es2@e00ti,dss-gate-clockxcntdss_ick_3430es2@e10ti,omap3-dss-interface-clockCntusbhost_120m_fck@1400ti,gate-clockwntusbhost_48m_fck@1400ti,dss-gate-clock4ntusbhost_ick@1410ti,omap3-dss-interface-clockCntclockdomainscore_l3_clkdmti,clockdomainyz{|}~dpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainjdpll4_clkdmti,clockdomain!wkup_clkdmti,clockdomain dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaindpll5_clkdmti,clockdomainmsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH ntdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `ntgpio@48310000ti,omap3-gpioH1gpio1ntgpio@49050000ti,omap3-gpioIgpio2ntgpio@49052000ti,omap3-gpioI gpio3ntgpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5ntgpio@49058000ti,omap3-gpioI"gpio6ntserial@4806a000ti,omap3-uartH H12txrxuart1lserial@4806c000ti,omap3-uartHI34txrxuart2lserial@49020000ti,omap3-uartIJ56txrxuart3lBdefaultPi2c@48070000 ti,omap3-i2cH8txrx+i2c1BdefaultPat24@50 at24,24c02 Pi2c@48072000 ti,omap3-i2cH 9txrx+i2c2i2c@48060000 ti,omap3-i2cH=txrx+i2c3BdefaultPat24@50 at24,24c02 Pmailbox@48094000ti,omap3-mailboxmailboxH @"4 disableddsp F Qspi@48098000ti,omap2-mcspiH A+mcspi1\@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3BdefaultPads7846@0BdefaultP ti,ads7846ju`   spi@4809a000ti,omap2-mcspiH B+mcspi2\ +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3\ tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4\FGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrx#BdefaultP0: F Ommc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrxBdefaultP:Xh0v+wlcore@2 ti,wl1271 Immc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp disabledmmu@5d000000ti,omap2-iommu]mmu_iva disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrxmcbsp1 txrxfck disabledmcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckickokBdefaultPmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrxmcbsp4txrxfck disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrxmcbsp5txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH  disabledtimer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12 usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phy 'ehci-phyohci@48064400ti,ohci-omap3HD Lehci@48064800 ti,ehci-omapHH M2gpmc@6e000000ti,omap3430-gpmcgpmcnrxtx7C+ -ntnand@0,0ti,omap2-nand  UdvswxxxxZ Z'AHP<jx{xZ+partition@0xloaderpartition@0x80000ubootpartition@0x260000uboot environment&partition@0x2a0000linux*@partition@0x6a0000rootfsjethernet@4,0smsc,lan9221smsc,lan9115BdefaultP  d( --j{Ax'KPK*AQ_lusb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hs dss@48050000 ti,omap3-dssHok dss_corefck+BdefaultPdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH ok dss_vencfckportendpointportendpointntssi-controller@48058000 ti,omap3-ssissi disabledHHsysgddGgdd_mpu+ssi-port@4805a000ti,omap3-ssi-portHHtxrx CDssi-port@4805b000ti,omap3-ssi-portHHtxrx EFam35x_otg_hs@5c040000ti,omap3-musb am35x_otg_hsokay\GmcBdefaultPethernet@0x5c000000ti,am3517-emac davinci_emacokay\CDEF| 3Fethernet@0x5c030000ti,davinci_mdio davinci_mdiookay\XB@+serial@4809e000ti,omap3-uartuart4 disabledH T76txrxlpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+%memory@80000000~memoryleds gpio-ledsBdefaultPledb cm-t3x:green I aheartbeathsusb1_power_regregulator-fixed hsusb1_vbus2Z2Zwpnthsusb2_power_regregulator-fixed hsusb2_vbus2Z2Zwpnthsusb1_phyusb-nop-xceivjBdefaultP nthsusb2_phyusb-nop-xceivjBdefaultP ntads7846-regregulator-fixed ads7846-reg2Z2Zntconnectordvi-connectordviportendpointntregulator-vmmcregulator-fixedvmmc2Z2Zntwl12xx_vmmc2regulator-fixedvw1271BdefaultPw@w@ wN ntwl12xx_vaux2regulator-fixedvwl1271_vaux2w@w@ntencoder ti,tfp410 BdefaultPports+port@0endpointntport@1endpointntaudio_ampregulator-fixed audio_ampBdefaultP regulator-vddvario-sb-t35regulator-fixed vddvariontregulator-vdd33a-sb-t35regulator-fixedvdd33ant compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3display0display1device_typeregclocksclock-namesclock-latencyinterruptsti,hwmodsstatusranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinslinux,phandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lock#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpagesize#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplywp-gpioscd-gpiosvmmc_aux-supplynon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-modephysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsremote-endpointti,channelsdata-linesti,davinci-ctrl-reg-offsetti,davinci-ctrl-mod-reg-offsetti,davinci-ctrl-ram-offsetti,davinci-ctrl-ram-sizeti,davinci-rmii-enlocal-mac-addressbus_freqlinux,default-triggerstartup-delay-usreset-gpiosenable-active-highpowerdown-gpiosenable-active-lowregulator-always-on