8( Egumstix,omap3-overo-tobiduogumstix,omap3-overoti,omap36xxti,omap3 +07OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuochosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8lcpux|cpus 'O 57pmu@54000000arm,cortex-a8-pmuxTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busxh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busx + pinmux@30 ti,omap3-padconfpinctrl-singlex08+:defaultHRXpinmux_uart2_pins `<>@BRXpinmux_i2c1_pins`RXpinmux_mmc1_pins0`RXpinmux_mmc2_pins0`(*,.02RXpinmux_w3cbw003c_pins`lR X pinmux_hsusb2_pins@`      RXpinmux_twl4030_pins`ARXpinmux_i2c3_pins`RXpinmux_uart3_pins`npRXscm_conf@270sysconsimple-busxp0+ p0RXpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapxtpbias_mmc_omap2430{pbias_mmc_omap2430w@-RXclocks+mcbsp5_mux_fck@68ti,composite-mux-clock|xhRXmcbsp5_fckti,composite-clock|RXmcbsp1_mux_fck@4ti,composite-mux-clock|xR X mcbsp1_fckti,composite-clock| RXmcbsp2_mux_fck@4ti,composite-mux-clock| xR X mcbsp2_fckti,composite-clock| RXmcbsp3_mux_fck@68ti,composite-mux-clock| xhRXmcbsp3_fckti,composite-clock|RXmcbsp4_mux_fck@68ti,composite-mux-clock| xhRXmcbsp4_fckti,composite-clock|RXclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singlex \+pinmux_twl4030_vpins `RXaes@480c5000 ti,omap3-aesaesxH PPABtxrxprm@48306000 ti,omap3-prmxH0`@ clocks+virt_16_8m_ck fixed-clockYRXosc_sys_ck@d40 ti,mux-clock|x @RXsys_ck@1270ti,divider-clock|xpRXsys_clkout1@d70ti,gate-clock|x pdpll3_x2_ckfixed-factor-clock| dpll3_m2x2_ckfixed-factor-clock| RXdpll4_x2_ckfixed-factor-clock| corex2_fckfixed-factor-clock| RXwkup_l4_ickfixed-factor-clock| RNXNcorex2_d3_fckfixed-factor-clock| RXcorex2_d5_fckfixed-factor-clock| RXclockdomainscm@48004000 ti,omap3-cmxH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockR@X@virt_12m_ck fixed-clockRXvirt_13m_ck fixed-clock]@RXvirt_19200000_ck fixed-clock$RXvirt_26000000_ck fixed-clockRXvirt_38_4m_ck fixed-clockIRXdpll4_ck@d00ti,omap3-dpll-per-j-type-clock|x D 0RXdpll4_m2_ck@d48ti,divider-clock|?x HR X dpll4_m2x2_mul_ckfixed-factor-clock|  R!X!dpll4_m2x2_ck@d00ti,hsdiv-gate-clock|!x *R"X"omap_96m_alwon_fckfixed-factor-clock|" R)X)dpll3_ck@d00ti,omap3-dpll-core-clock|x @ 0RXdpll3_m3_ck@1140ti,divider-clock|x@R#X#dpll3_m3x2_mul_ckfixed-factor-clock|# R$X$dpll3_m3x2_ck@d00ti,hsdiv-gate-clock|$ x *R%X%emu_core_alwon_ckfixed-factor-clock|% RbXbsys_altclk fixed-clockR.X.mcbsp_clks fixed-clockRXdpll3_m2_ck@d40ti,divider-clock|x @RXcore_ckfixed-factor-clock| R&X&dpll1_fck@940ti,divider-clock|&x @R'X'dpll1_ck@904ti,omap3-dpll-clock|'x  $ @ 4RXdpll1_x2_ckfixed-factor-clock| R(X(dpll1_x2m2_ck@944ti,divider-clock|(x DR<X<cm_96m_fckfixed-factor-clock|) R*X*omap_96m_fck@d40 ti,mux-clock|*x @REXEdpll4_m3_ck@e40ti,divider-clock| x@R+X+dpll4_m3x2_mul_ckfixed-factor-clock|+ R,X,dpll4_m3x2_ck@d00ti,hsdiv-gate-clock|,x *R-X-omap_54m_fck@d40 ti,mux-clock|-.x @R8X8cm_96m_d2_fckfixed-factor-clock|* R/X/omap_48m_fck@d40 ti,mux-clock|/.x @R0X0omap_12m_fckfixed-factor-clock|0 RGXGdpll4_m4_ck@e40ti,divider-clock| x@R1X1dpll4_m4x2_mul_ckti,fixed-factor-clock|1@N[R2X2dpll4_m4x2_ck@d00ti,gate-clock|2x *[RXdpll4_m5_ck@f40ti,divider-clock|?x@R3X3dpll4_m5x2_mul_ckti,fixed-factor-clock|3@N[R4X4dpll4_m5x2_ck@d00ti,hsdiv-gate-clock|4x *[RjXjdpll4_m6_ck@1140ti,divider-clock|?x@R5X5dpll4_m6x2_mul_ckfixed-factor-clock|5 R6X6dpll4_m6x2_ck@d00ti,hsdiv-gate-clock|6x *R7X7emu_per_alwon_ckfixed-factor-clock|7 RcXcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock|&x pR9X9clkout2_src_mux_ck@d70ti,composite-mux-clock|&*8x pR:X:clkout2_src_ckti,composite-clock|9:R;X;sys_clkout2@d70ti,divider-clock|;@x pnmpu_ckfixed-factor-clock|< R=X=arm_fck@924ti,divider-clock|=x $emu_mpu_alwon_ckfixed-factor-clock|= RdXdl3_ick@a40ti,divider-clock|&x @R>X>l4_ick@a40ti,divider-clock|>x @R?X?rm_ick@c40ti,divider-clock|?x @gpt10_gate_fck@a00ti,composite-gate-clock| x RAXAgpt10_mux_fck@a40ti,composite-mux-clock|@x @RBXBgpt10_fckti,composite-clock|ABgpt11_gate_fck@a00ti,composite-gate-clock| x RCXCgpt11_mux_fck@a40ti,composite-mux-clock|@x @RDXDgpt11_fckti,composite-clock|CDcore_96m_fckfixed-factor-clock|E RXmmchs2_fck@a00ti,wait-gate-clock|x RXmmchs1_fck@a00ti,wait-gate-clock|x RXi2c3_fck@a00ti,wait-gate-clock|x RXi2c2_fck@a00ti,wait-gate-clock|x RXi2c1_fck@a00ti,wait-gate-clock|x RXmcbsp5_gate_fck@a00ti,composite-gate-clock| x RXmcbsp1_gate_fck@a00ti,composite-gate-clock| x R X core_48m_fckfixed-factor-clock|0 RFXFmcspi4_fck@a00ti,wait-gate-clock|Fx RXmcspi3_fck@a00ti,wait-gate-clock|Fx RXmcspi2_fck@a00ti,wait-gate-clock|Fx RXmcspi1_fck@a00ti,wait-gate-clock|Fx RXuart2_fck@a00ti,wait-gate-clock|Fx RXuart1_fck@a00ti,wait-gate-clock|Fx  RXcore_12m_fckfixed-factor-clock|G RHXHhdq_fck@a00ti,wait-gate-clock|Hx RXcore_l3_ickfixed-factor-clock|> RIXIsdrc_ick@a10ti,wait-gate-clock|Ix RXgpmc_fckfixed-factor-clock|I core_l4_ickfixed-factor-clock|? RJXJmmchs2_ick@a10ti,omap3-interface-clock|Jx RXmmchs1_ick@a10ti,omap3-interface-clock|Jx RXhdq_ick@a10ti,omap3-interface-clock|Jx RXmcspi4_ick@a10ti,omap3-interface-clock|Jx RXmcspi3_ick@a10ti,omap3-interface-clock|Jx RXmcspi2_ick@a10ti,omap3-interface-clock|Jx RXmcspi1_ick@a10ti,omap3-interface-clock|Jx RXi2c3_ick@a10ti,omap3-interface-clock|Jx RXi2c2_ick@a10ti,omap3-interface-clock|Jx RXi2c1_ick@a10ti,omap3-interface-clock|Jx RXuart2_ick@a10ti,omap3-interface-clock|Jx RXuart1_ick@a10ti,omap3-interface-clock|Jx  RXgpt11_ick@a10ti,omap3-interface-clock|Jx  RXgpt10_ick@a10ti,omap3-interface-clock|Jx  RXmcbsp5_ick@a10ti,omap3-interface-clock|Jx  RXmcbsp1_ick@a10ti,omap3-interface-clock|Jx  RXomapctrl_ick@a10ti,omap3-interface-clock|Jx RXdss_tv_fck@e00ti,gate-clock|8xRXdss_96m_fck@e00ti,gate-clock|ExRXdss2_alwon_fck@e00ti,gate-clock|xRXdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock|x RKXKgpt1_mux_fck@c40ti,composite-mux-clock|@x @RLXLgpt1_fckti,composite-clock|KLaes2_ick@a10ti,omap3-interface-clock|Jx RXwkup_32k_fckfixed-factor-clock|@ RMXMgpio1_dbck@c00ti,gate-clock|Mx RXsha12_ick@a10ti,omap3-interface-clock|Jx RXwdt2_fck@c00ti,wait-gate-clock|Mx RXwdt2_ick@c10ti,omap3-interface-clock|Nx RXwdt1_ick@c10ti,omap3-interface-clock|Nx RXgpio1_ick@c10ti,omap3-interface-clock|Nx RXomap_32ksync_ick@c10ti,omap3-interface-clock|Nx RXgpt12_ick@c10ti,omap3-interface-clock|Nx RXgpt1_ick@c10ti,omap3-interface-clock|Nx RXper_96m_fckfixed-factor-clock|) R X per_48m_fckfixed-factor-clock|0 ROXOuart3_fck@1000ti,wait-gate-clock|Ox RXgpt2_gate_fck@1000ti,composite-gate-clock|xRPXPgpt2_mux_fck@1040ti,composite-mux-clock|@x@RQXQgpt2_fckti,composite-clock|PQgpt3_gate_fck@1000ti,composite-gate-clock|xRRXRgpt3_mux_fck@1040ti,composite-mux-clock|@x@RSXSgpt3_fckti,composite-clock|RSgpt4_gate_fck@1000ti,composite-gate-clock|xRTXTgpt4_mux_fck@1040ti,composite-mux-clock|@x@RUXUgpt4_fckti,composite-clock|TUgpt5_gate_fck@1000ti,composite-gate-clock|xRVXVgpt5_mux_fck@1040ti,composite-mux-clock|@x@RWXWgpt5_fckti,composite-clock|VWgpt6_gate_fck@1000ti,composite-gate-clock|xRXXXgpt6_mux_fck@1040ti,composite-mux-clock|@x@RYXYgpt6_fckti,composite-clock|XYgpt7_gate_fck@1000ti,composite-gate-clock|xRZXZgpt7_mux_fck@1040ti,composite-mux-clock|@x@R[X[gpt7_fckti,composite-clock|Z[gpt8_gate_fck@1000ti,composite-gate-clock| xR\X\gpt8_mux_fck@1040ti,composite-mux-clock|@x@R]X]gpt8_fckti,composite-clock|\]gpt9_gate_fck@1000ti,composite-gate-clock| xR^X^gpt9_mux_fck@1040ti,composite-mux-clock|@x@R_X_gpt9_fckti,composite-clock|^_per_32k_alwon_fckfixed-factor-clock|@ R`X`gpio6_dbck@1000ti,gate-clock|`xRXgpio5_dbck@1000ti,gate-clock|`xRXgpio4_dbck@1000ti,gate-clock|`xRXgpio3_dbck@1000ti,gate-clock|`xRXgpio2_dbck@1000ti,gate-clock|`x RXwdt3_fck@1000ti,wait-gate-clock|`x RXper_l4_ickfixed-factor-clock|? RaXagpio6_ick@1010ti,omap3-interface-clock|axRXgpio5_ick@1010ti,omap3-interface-clock|axRXgpio4_ick@1010ti,omap3-interface-clock|axRXgpio3_ick@1010ti,omap3-interface-clock|axRXgpio2_ick@1010ti,omap3-interface-clock|ax RXwdt3_ick@1010ti,omap3-interface-clock|ax RXuart3_ick@1010ti,omap3-interface-clock|ax RXuart4_ick@1010ti,omap3-interface-clock|axRXgpt9_ick@1010ti,omap3-interface-clock|ax RXgpt8_ick@1010ti,omap3-interface-clock|ax RXgpt7_ick@1010ti,omap3-interface-clock|axRXgpt6_ick@1010ti,omap3-interface-clock|axRXgpt5_ick@1010ti,omap3-interface-clock|axRXgpt4_ick@1010ti,omap3-interface-clock|axRXgpt3_ick@1010ti,omap3-interface-clock|axRXgpt2_ick@1010ti,omap3-interface-clock|axRXmcbsp2_ick@1010ti,omap3-interface-clock|axRXmcbsp3_ick@1010ti,omap3-interface-clock|axRXmcbsp4_ick@1010ti,omap3-interface-clock|axRXmcbsp2_gate_fck@1000ti,composite-gate-clock|xR X mcbsp3_gate_fck@1000ti,composite-gate-clock|xRXmcbsp4_gate_fck@1000ti,composite-gate-clock|xRXemu_src_mux_ck@1140 ti,mux-clock|bcdx@ReXeemu_src_ckti,clkdm-gate-clock|eRfXfpclk_fck@1140ti,divider-clock|fx@pclkx2_fck@1140ti,divider-clock|fx@atclk_fck@1140ti,divider-clock|fx@traceclk_src_fck@1140 ti,mux-clock|bcdx@RgXgtraceclk_fck@1140ti,divider-clock|g x@secure_32k_fck fixed-clockRhXhgpt12_fckfixed-factor-clock|h wdt1_fckfixed-factor-clock|h security_l4_ick2fixed-factor-clock|? RiXiaes1_ick@a14ti,omap3-interface-clock|ix rng_ick@a14ti,omap3-interface-clock|ix sha11_ick@a14ti,omap3-interface-clock|ix des1_ick@a14ti,omap3-interface-clock|ix cam_mclk@f00ti,gate-clock|jx[cam_ick@f10!ti,omap3-no-wait-interface-clock|?xRXcsi2_96m_fck@f00ti,gate-clock|xRXsecurity_l3_ickfixed-factor-clock|> RkXkpka_ick@a14ti,omap3-interface-clock|kx icr_ick@a10ti,omap3-interface-clock|Jx des2_ick@a10ti,omap3-interface-clock|Jx mspro_ick@a10ti,omap3-interface-clock|Jx mailboxes_ick@a10ti,omap3-interface-clock|Jx ssi_l4_ickfixed-factor-clock|? RrXrsr1_fck@c00ti,wait-gate-clock|x sr2_fck@c00ti,wait-gate-clock|x sr_l4_ickfixed-factor-clock|? dpll2_fck@40ti,divider-clock|&x@RlXldpll2_ck@4ti,omap3-dpll-clock|lx$@4RmXmdpll2_m2_ck@44ti,divider-clock|mxDRnXniva2_ck@0ti,wait-gate-clock|nxRXmodem_fck@a00ti,omap3-interface-clock|x RXsad2d_ick@a10ti,omap3-interface-clock|>x RXmad2d_ick@a18ti,omap3-interface-clock|>x RXmspro_fck@a00ti,wait-gate-clock|x ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock|x RoXossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock|x @$RpXpssi_ssr_fck_3430es2ti,composite-clock|opRqXqssi_sst_fck_3430es2fixed-factor-clock|q RXhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock|Ix RXssi_ick_3430es2@a10ti,omap3-ssi-interface-clock|rx RXusim_gate_fck@c00ti,composite-gate-clock|E x R}X}sys_d2_ckfixed-factor-clock| RtXtomap_96m_d2_fckfixed-factor-clock|E RuXuomap_96m_d4_fckfixed-factor-clock|E RvXvomap_96m_d8_fckfixed-factor-clock|E RwXwomap_96m_d10_fckfixed-factor-clock|E RxXxdpll5_m2_d4_ckfixed-factor-clock|s RyXydpll5_m2_d8_ckfixed-factor-clock|s RzXzdpll5_m2_d16_ckfixed-factor-clock|s R{X{dpll5_m2_d20_ckfixed-factor-clock|s R|X|usim_mux_fck@c40ti,composite-mux-clock(|tuvwxyz{|x @R~X~usim_fckti,composite-clock|}~usim_ick@c10ti,omap3-interface-clock|Nx  RXdpll5_ck@d04ti,omap3-dpll-clock|x  $ L 4RXdpll5_m2_ck@d50ti,divider-clock|x PRsXssgx_gate_fck@b00ti,composite-gate-clock|&x RXcore_d3_ckfixed-factor-clock|& RXcore_d4_ckfixed-factor-clock|& RXcore_d6_ckfixed-factor-clock|& RXomap_192m_alwon_fckfixed-factor-clock|" RXcore_d2_ckfixed-factor-clock|& RXsgx_mux_fck@b40ti,composite-mux-clock |*x @RXsgx_fckti,composite-clock|sgx_ick@b10ti,wait-gate-clock|>x RXcpefuse_fck@a08ti,gate-clock|x RXts_fck@a08ti,gate-clock|@x RXusbtll_fck@a08ti,wait-gate-clock|sx RXusbtll_ick@a18ti,omap3-interface-clock|Jx RXmmchs3_ick@a10ti,omap3-interface-clock|Jx RXmmchs3_fck@a00ti,wait-gate-clock|x RXdss1_alwon_fck_3430es2@e00ti,dss-gate-clock|x[RXdss_ick_3430es2@e10ti,omap3-dss-interface-clock|?xRXusbhost_120m_fck@1400ti,gate-clock|sxRXusbhost_48m_fck@1400ti,dss-gate-clock|0xRXusbhost_ick@1410ti,omap3-dss-interface-clock|?xRXuart4_fck@1000ti,wait-gate-clock|OxRXclockdomainscore_l3_clkdmti,clockdomain|dpll3_clkdmti,clockdomain|dpll1_clkdmti,clockdomain|per_clkdmti,clockdomainl|emu_clkdmti,clockdomain|fdpll4_clkdmti,clockdomain|wkup_clkdmti,clockdomain$|dss_clkdmti,clockdomain|core_l4_clkdmti,clockdomain|cam_clkdmti,clockdomain|iva2_clkdmti,clockdomain|dpll2_clkdmti,clockdomain|md2d_clkdmti,clockdomain |dpll5_clkdmti,clockdomain|sgx_clkdmti,clockdomain|usbhost_clkdmti,clockdomain |counter@48320000ti,omap-counter32kxH2  counter_32kinterrupt-controller@48200000ti,omap3-intcxH RXdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaxH`  `RXgpio@48310000ti,omap3-gpioxH1gpio1R X gpio@49050000ti,omap3-gpioxIgpio2R X gpio@49052000ti,omap3-gpioxI gpio3RXgpio@49054000ti,omap3-gpioxI@ gpio4gpio@49056000ti,omap3-gpioxI`!gpio5gpio@49058000ti,omap3-gpioxI"gpio6RXserial@4806a000ti,omap3-uartxH H12txrxuart1lserial@4806c000ti,omap3-uartxHI34txrxuart2l:defaultHserial@49020000ti,omap3-uartxIJn56txrxuart3l:defaultHi2c@48070000 ti,omap3-i2cxH8txrx+i2c1:defaultH'@twl@48xH  ti,twl4030:defaultHaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci %watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0RXregulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5RXregulator-vusb1v8ti,twl4030-vusb1v8RXregulator-vusb3v1ti,twl4030-vusb3v1RXregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio3twl4030-usbti,twl4030-usb ?M[irRXpwmti,twl4030-pwm}pwmledti,twl4030-pwmled}RXpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypadmadcti,twl4030-madci2c@48072000 ti,omap3-i2cxH 9txrx+i2c2 disabledi2c@48060000 ti,omap3-i2cxH=txrx+i2c3:defaultHeeprom@51 atmel,24c01xQlis33de@1dst,lis33dest,lis3lv02dx  . @ R`n}xx&& disabledmailbox@48094000ti,omap3-mailboxmailboxxH @".@dsp R ]spi@48098000ti,omap2-mcspixH A+mcspi1h@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspixH B+mcspi2h +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspixH [+mcspi3h tx0rx0tx1rx1spi@480ba000ti,omap2-mcspixH 0+mcspi4hFGtx0rx01w@480b2000 ti,omap3-1wxH :hdq1wmmc@4809c000ti,omap3-hsmmcxH Smmc1v=>txrx:defaultHmmc@480b4000ti,omap3-hsmmcxH @Vmmc2/0txrx:defaultHmmc@480ad000ti,omap3-hsmmcxH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuxH mmu_ispRXmmu@5d000000ti,omap2-iommux]mmu_iva disabledwdt@48314000 ti,omap3-wdtxH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspxH@mpu ;< commontxrxmcbsp1 txrx|fck disabledmcbsp@49022000ti,omap3-mcbspxI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx|fckickokayRXmcbsp@49024000ti,omap3-mcbspxI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx|fckick disabledmcbsp@49026000ti,omap3-mcbspxI`mpu 67 commontxrxmcbsp4txrx|fck disabledmcbsp@48096000ti,omap3-mcbspxH `mpu QR commontxrxmcbsp5txrx|fck disabledsham@480c3000ti,omap3-shamshamxH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_corexH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaxH timer@48318000ti,omap3430-timerxH1%timer1$timer@49032000ti,omap3430-timerxI &timer2timer@49034000ti,omap3430-timerxI@'timer3timer@49036000ti,omap3430-timerxI`(timer4timer@49038000ti,omap3430-timerxI)timer53timer@4903a000ti,omap3430-timerxI*timer63timer@4903c000ti,omap3430-timerxI+timer73timer@4903e000ti,omap3430-timerxI,timer8@3timer@49040000ti,omap3430-timerxI-timer9@timer@48086000ti,omap3430-timerxH`.timer10@timer@48088000ti,omap3430-timerxH/timer11@timer@48304000ti,omap3430-timerxH0@_timer12$Musbhstll@48062000 ti,usbhs-tllxH N usb_tll_hsusbhshost@48064000ti,usbhs-hostxH@ usb_host_hs+ ]ehci-phyohci@48064400ti,ohci-omap3xHD Lehci@48064800 ti,ehci-omapxHH Mhgpmc@6e000000ti,omap3430-gpmcgpmcxnrxtxmy+00+,RXnand@0,0ti,omap2-nandmicron,mt29c4g96maz x bch8,,"0,C(R6a@pRR(+partition@0SPLxpartition@80000U-Bootxpartition@1c0000 Environmentx$partition@280000Kernelx(partition@780000 Filesystemxethernet@gpmcsmsc,lan9221smsc,lan9115*$ 0 R*C$p<6a$,*F`z x ethernet@4,0smsc,lan9221smsc,lan9115*$ 0 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hsusb2_power_regregulator-fixed {hsusb2_vbusLK@LK@  p R X hsusb2_phyusb-nop-xceiv   RXregulator-w3cbw003c-npoweronregulator-fixed{regulator-w3cbw003c-npoweron2Z2Z   RXregulator-w3cbw003c-wifi-nreset:defaultH  regulator-fixed {regulator-w3cbw003c-wifi-nreset2Z2Z   'RXregulator-w3cbw003c-bt-nresetregulator-fixed{regulator-w3cbw003c-bt-nreset2Z2Z  'RXlis33-3v3-regregulator-fixed{lis33-3v3-reg2Z2ZRXlis33-1v8-regregulator-fixed{lis33-1v8-regw@w@RXregulator-vddvarioregulator-fixed {vddvario RXregulator-vdd33aregulator-fixed{vdd33a RX compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0linux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplyvmmc_aux-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-modephysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplyregulator-always-on