8( "Lti,omap3-evmti,omap3 +7TI OMAP35XX EVM (TMDSEVM3530)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+ *GMpinmux_twl4030_pinsUAGMscm_conf@270sysconsimple-busyp0+ p0GMpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyipbias_mmc_omap2430ppbias_mmc_omap2430w@-GMclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhGMmcbsp5_fckti,composite-clock}GMmcbsp1_mux_fck@4ti,composite-mux-clock}yG M mcbsp1_fckti,composite-clock} GMmcbsp2_mux_fck@4ti,composite-mux-clock} yG M mcbsp2_fckti,composite-clock} GMmcbsp3_mux_fck@68ti,composite-mux-clock} yhGMmcbsp3_fckti,composite-clock}GMmcbsp4_mux_fck@68ti,composite-mux-clock} yhGMmcbsp4_fckti,composite-clock}GMclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+ *pinmux_twl4030_vpins UGMaes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYGMosc_sys_ck@d40 ti,mux-clock}y @GMsys_ck@1270ti,divider-clock}ypGMsys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock} dpll3_m2x2_ckfixed-factor-clock} GMdpll4_x2_ckfixed-factor-clock} corex2_fckfixed-factor-clock} GMwkup_l4_ickfixed-factor-clock} GNMNcorex2_d3_fckfixed-factor-clock} GMcorex2_d5_fckfixed-factor-clock} GMclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockG@M@virt_12m_ck fixed-clockGMvirt_13m_ck fixed-clock]@GMvirt_19200000_ck fixed-clock$GMvirt_26000000_ck fixed-clockGMvirt_38_4m_ck fixed-clockIGMdpll4_ck@d00ti,omap3-dpll-per-clock}y D 0GMdpll4_m2_ck@d48ti,divider-clock}?y HG M dpll4_m2x2_mul_ckfixed-factor-clock}  G!M!dpll4_m2x2_ck@d00ti,gate-clock}!y G"M"omap_96m_alwon_fckfixed-factor-clock}" G)M)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0GMdpll3_m3_ck@1140ti,divider-clock}y@G#M#dpll3_m3x2_mul_ckfixed-factor-clock}# G$M$dpll3_m3x2_ck@d00ti,gate-clock}$ y G%M%emu_core_alwon_ckfixed-factor-clock}% GbMbsys_altclk fixed-clockG.M.mcbsp_clks fixed-clockGMdpll3_m2_ck@d40ti,divider-clock}y @GMcore_ckfixed-factor-clock} G&M&dpll1_fck@940ti,divider-clock}&y @G'M'dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 4GMdpll1_x2_ckfixed-factor-clock} G(M(dpll1_x2m2_ck@944ti,divider-clock}(y DG<M<cm_96m_fckfixed-factor-clock}) G*M*omap_96m_fck@d40 ti,mux-clock}*y @GEMEdpll4_m3_ck@e40ti,divider-clock} y@G+M+dpll4_m3x2_mul_ckfixed-factor-clock}+ G,M,dpll4_m3x2_ck@d00ti,gate-clock},y G-M-omap_54m_fck@d40 ti,mux-clock}-.y @G8M8cm_96m_d2_fckfixed-factor-clock}* G/M/omap_48m_fck@d40 ti,mux-clock}/.y @G0M0omap_12m_fckfixed-factor-clock}0 GGMGdpll4_m4_ck@e40ti,divider-clock} y@G1M1dpll4_m4x2_mul_ckti,fixed-factor-clock}15CPG2M2dpll4_m4x2_ck@d00ti,gate-clock}2y PGMdpll4_m5_ck@f40ti,divider-clock}?y@G3M3dpll4_m5x2_mul_ckti,fixed-factor-clock}35CPG4M4dpll4_m5x2_ck@d00ti,gate-clock}4y PGjMjdpll4_m6_ck@1140ti,divider-clock}?y@G5M5dpll4_m6x2_mul_ckfixed-factor-clock}5 G6M6dpll4_m6x2_ck@d00ti,gate-clock}6y G7M7emu_per_alwon_ckfixed-factor-clock}7 GcMcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y pG9M9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y pG:M:clkout2_src_ckti,composite-clock}9:G;M;sys_clkout2@d70ti,divider-clock};@y pcmpu_ckfixed-factor-clock}< G=M=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}= GdMdl3_ick@a40ti,divider-clock}&y @G>M>l4_ick@a40ti,divider-clock}>y @G?M?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y GAMAgpt10_mux_fck@a40ti,composite-mux-clock}@y @GBMBgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y GCMCgpt11_mux_fck@a40ti,composite-mux-clock}@y @GDMDgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}E GMmmchs2_fck@a00ti,wait-gate-clock}y GMmmchs1_fck@a00ti,wait-gate-clock}y GMi2c3_fck@a00ti,wait-gate-clock}y GMi2c2_fck@a00ti,wait-gate-clock}y GMi2c1_fck@a00ti,wait-gate-clock}y GMmcbsp5_gate_fck@a00ti,composite-gate-clock} y GMmcbsp1_gate_fck@a00ti,composite-gate-clock} y G M core_48m_fckfixed-factor-clock}0 GFMFmcspi4_fck@a00ti,wait-gate-clock}Fy GMmcspi3_fck@a00ti,wait-gate-clock}Fy GMmcspi2_fck@a00ti,wait-gate-clock}Fy GMmcspi1_fck@a00ti,wait-gate-clock}Fy GMuart2_fck@a00ti,wait-gate-clock}Fy GMuart1_fck@a00ti,wait-gate-clock}Fy  GMcore_12m_fckfixed-factor-clock}G GHMHhdq_fck@a00ti,wait-gate-clock}Hy GMcore_l3_ickfixed-factor-clock}> GIMIsdrc_ick@a10ti,wait-gate-clock}Iy GMgpmc_fckfixed-factor-clock}I core_l4_ickfixed-factor-clock}? GJMJmmchs2_ick@a10ti,omap3-interface-clock}Jy GMmmchs1_ick@a10ti,omap3-interface-clock}Jy GMhdq_ick@a10ti,omap3-interface-clock}Jy GMmcspi4_ick@a10ti,omap3-interface-clock}Jy GMmcspi3_ick@a10ti,omap3-interface-clock}Jy GMmcspi2_ick@a10ti,omap3-interface-clock}Jy GMmcspi1_ick@a10ti,omap3-interface-clock}Jy GMi2c3_ick@a10ti,omap3-interface-clock}Jy GMi2c2_ick@a10ti,omap3-interface-clock}Jy GMi2c1_ick@a10ti,omap3-interface-clock}Jy GMuart2_ick@a10ti,omap3-interface-clock}Jy GMuart1_ick@a10ti,omap3-interface-clock}Jy  GMgpt11_ick@a10ti,omap3-interface-clock}Jy  GMgpt10_ick@a10ti,omap3-interface-clock}Jy  GMmcbsp5_ick@a10ti,omap3-interface-clock}Jy  GMmcbsp1_ick@a10ti,omap3-interface-clock}Jy  GMomapctrl_ick@a10ti,omap3-interface-clock}Jy GMdss_tv_fck@e00ti,gate-clock}8yGMdss_96m_fck@e00ti,gate-clock}EyGMdss2_alwon_fck@e00ti,gate-clock}yGMdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y GKMKgpt1_mux_fck@c40ti,composite-mux-clock}@y @GLMLgpt1_fckti,composite-clock}KLaes2_ick@a10ti,omap3-interface-clock}Jy GMwkup_32k_fckfixed-factor-clock}@ GMMMgpio1_dbck@c00ti,gate-clock}My GMsha12_ick@a10ti,omap3-interface-clock}Jy GMwdt2_fck@c00ti,wait-gate-clock}My GMwdt2_ick@c10ti,omap3-interface-clock}Ny GMwdt1_ick@c10ti,omap3-interface-clock}Ny GMgpio1_ick@c10ti,omap3-interface-clock}Ny GMomap_32ksync_ick@c10ti,omap3-interface-clock}Ny GMgpt12_ick@c10ti,omap3-interface-clock}Ny GMgpt1_ick@c10ti,omap3-interface-clock}Ny GMper_96m_fckfixed-factor-clock}) G M per_48m_fckfixed-factor-clock}0 GOMOuart3_fck@1000ti,wait-gate-clock}Oy GMgpt2_gate_fck@1000ti,composite-gate-clock}yGPMPgpt2_mux_fck@1040ti,composite-mux-clock}@y@GQMQgpt2_fckti,composite-clock}PQgpt3_gate_fck@1000ti,composite-gate-clock}yGRMRgpt3_mux_fck@1040ti,composite-mux-clock}@y@GSMSgpt3_fckti,composite-clock}RSgpt4_gate_fck@1000ti,composite-gate-clock}yGTMTgpt4_mux_fck@1040ti,composite-mux-clock}@y@GUMUgpt4_fckti,composite-clock}TUgpt5_gate_fck@1000ti,composite-gate-clock}yGVMVgpt5_mux_fck@1040ti,composite-mux-clock}@y@GWMWgpt5_fckti,composite-clock}VWgpt6_gate_fck@1000ti,composite-gate-clock}yGXMXgpt6_mux_fck@1040ti,composite-mux-clock}@y@GYMYgpt6_fckti,composite-clock}XYgpt7_gate_fck@1000ti,composite-gate-clock}yGZMZgpt7_mux_fck@1040ti,composite-mux-clock}@y@G[M[gpt7_fckti,composite-clock}Z[gpt8_gate_fck@1000ti,composite-gate-clock} yG\M\gpt8_mux_fck@1040ti,composite-mux-clock}@y@G]M]gpt8_fckti,composite-clock}\]gpt9_gate_fck@1000ti,composite-gate-clock} yG^M^gpt9_mux_fck@1040ti,composite-mux-clock}@y@G_M_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@ G`M`gpio6_dbck@1000ti,gate-clock}`yGMgpio5_dbck@1000ti,gate-clock}`yGMgpio4_dbck@1000ti,gate-clock}`yGMgpio3_dbck@1000ti,gate-clock}`yGMgpio2_dbck@1000ti,gate-clock}`y GMwdt3_fck@1000ti,wait-gate-clock}`y GMper_l4_ickfixed-factor-clock}? GaMagpio6_ick@1010ti,omap3-interface-clock}ayGMgpio5_ick@1010ti,omap3-interface-clock}ayGMgpio4_ick@1010ti,omap3-interface-clock}ayGMgpio3_ick@1010ti,omap3-interface-clock}ayGMgpio2_ick@1010ti,omap3-interface-clock}ay GMwdt3_ick@1010ti,omap3-interface-clock}ay GMuart3_ick@1010ti,omap3-interface-clock}ay GMuart4_ick@1010ti,omap3-interface-clock}ayGMgpt9_ick@1010ti,omap3-interface-clock}ay GMgpt8_ick@1010ti,omap3-interface-clock}ay GMgpt7_ick@1010ti,omap3-interface-clock}ayGMgpt6_ick@1010ti,omap3-interface-clock}ayGMgpt5_ick@1010ti,omap3-interface-clock}ayGMgpt4_ick@1010ti,omap3-interface-clock}ayGMgpt3_ick@1010ti,omap3-interface-clock}ayGMgpt2_ick@1010ti,omap3-interface-clock}ayGMmcbsp2_ick@1010ti,omap3-interface-clock}ayGMmcbsp3_ick@1010ti,omap3-interface-clock}ayGMmcbsp4_ick@1010ti,omap3-interface-clock}ayGMmcbsp2_gate_fck@1000ti,composite-gate-clock}yG M mcbsp3_gate_fck@1000ti,composite-gate-clock}yGMmcbsp4_gate_fck@1000ti,composite-gate-clock}yGMemu_src_mux_ck@1140 ti,mux-clock}bcdy@GeMeemu_src_ckti,clkdm-gate-clock}eGfMfpclk_fck@1140ti,divider-clock}fy@pclkx2_fck@1140ti,divider-clock}fy@atclk_fck@1140ti,divider-clock}fy@traceclk_src_fck@1140 ti,mux-clock}bcdy@GgMgtraceclk_fck@1140ti,divider-clock}g y@secure_32k_fck fixed-clockGhMhgpt12_fckfixed-factor-clock}h wdt1_fckfixed-factor-clock}h security_l4_ick2fixed-factor-clock}? GiMiaes1_ick@a14ti,omap3-interface-clock}iy rng_ick@a14ti,omap3-interface-clock}iy sha11_ick@a14ti,omap3-interface-clock}iy des1_ick@a14ti,omap3-interface-clock}iy cam_mclk@f00ti,gate-clock}jyPcam_ick@f10!ti,omap3-no-wait-interface-clock}?yGMcsi2_96m_fck@f00ti,gate-clock}yGMsecurity_l3_ickfixed-factor-clock}> GkMkpka_ick@a14ti,omap3-interface-clock}ky icr_ick@a10ti,omap3-interface-clock}Jy des2_ick@a10ti,omap3-interface-clock}Jy mspro_ick@a10ti,omap3-interface-clock}Jy mailboxes_ick@a10ti,omap3-interface-clock}Jy ssi_l4_ickfixed-factor-clock}? GrMrsr1_fck@c00ti,wait-gate-clock}y sr2_fck@c00ti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}? dpll2_fck@40ti,divider-clock}&y@GlMldpll2_ck@4ti,omap3-dpll-clock}ly$@4yGmMmdpll2_m2_ck@44ti,divider-clock}myDGnMniva2_ck@0ti,wait-gate-clock}nyGMmodem_fck@a00ti,omap3-interface-clock}y GMsad2d_ick@a10ti,omap3-interface-clock}>y GMmad2d_ick@a18ti,omap3-interface-clock}>y GMmspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}y GoMossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}y @$GpMpssi_ssr_fck_3430es2ti,composite-clock}opGqMqssi_sst_fck_3430es2fixed-factor-clock}q GMhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Iy GMssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}ry GMusim_gate_fck@c00ti,composite-gate-clock}E y G}M}sys_d2_ckfixed-factor-clock} GtMtomap_96m_d2_fckfixed-factor-clock}E GuMuomap_96m_d4_fckfixed-factor-clock}E GvMvomap_96m_d8_fckfixed-factor-clock}E GwMwomap_96m_d10_fckfixed-factor-clock}E  GxMxdpll5_m2_d4_ckfixed-factor-clock}s GyMydpll5_m2_d8_ckfixed-factor-clock}s GzMzdpll5_m2_d16_ckfixed-factor-clock}s G{M{dpll5_m2_d20_ckfixed-factor-clock}s G|M|usim_mux_fck@c40ti,composite-mux-clock(}tuvwxyz{|y @G~M~usim_fckti,composite-clock}}~usim_ick@c10ti,omap3-interface-clock}Ny  GMdpll5_ck@d04ti,omap3-dpll-clock}y  $ L 4yGMdpll5_m2_ck@d50ti,divider-clock}y PGsMssgx_gate_fck@b00ti,composite-gate-clock}&y GMcore_d3_ckfixed-factor-clock}& GMcore_d4_ckfixed-factor-clock}& GMcore_d6_ckfixed-factor-clock}& GMomap_192m_alwon_fckfixed-factor-clock}" GMcore_d2_ckfixed-factor-clock}& GMsgx_mux_fck@b40ti,composite-mux-clock }*y @GMsgx_fckti,composite-clock}sgx_ick@b10ti,wait-gate-clock}>y GMcpefuse_fck@a08ti,gate-clock}y GMts_fck@a08ti,gate-clock}@y GMusbtll_fck@a08ti,wait-gate-clock}sy GMusbtll_ick@a18ti,omap3-interface-clock}Jy GMmmchs3_ick@a10ti,omap3-interface-clock}Jy GMmmchs3_fck@a00ti,wait-gate-clock}y GMdss1_alwon_fck_3430es2@e00ti,dss-gate-clock}yPGMdss_ick_3430es2@e10ti,omap3-dss-interface-clock}?yGMusbhost_120m_fck@1400ti,gate-clock}syGMusbhost_48m_fck@1400ti,dss-gate-clock}0yGMusbhost_ick@1410ti,omap3-dss-interface-clock}?yGMclockdomainscore_l3_clkdmti,clockdomain}dpll3_clkdmti,clockdomain}dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}fdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}md2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}sgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }counter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH GMdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmayH`  `GMgpio@48310000ti,omap3-gpioyH1gpio1GMgpio@49050000ti,omap3-gpioyIgpio2gpio@49052000ti,omap3-gpioyI gpio3gpio@49054000ti,omap3-gpioyI@ gpio4gpio@49056000ti,omap3-gpioyI`!gpio5GMgpio@49058000ti,omap3-gpioyI"gpio6GMserial@4806a000ti,omap3-uartyH H12txrxuart1lserial@4806c000ti,omap3-uartyHI34txrxuart2lserial@49020000ti,omap3-uartyIJ56txrxuart3li2c@48070000 ti,omap3-i2cyH8txrx+i2c1'@twl@48yH  ti,twl4030default(rtcti,twl4030-rtc bciti,twl4030-bci 2watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' GMregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0GMregulator-vmmc2ti,twl4030-vmmc2:0GMregulator-vusb1v5ti,twl4030-vusb1v5GMregulator-vusb1v8ti,twl4030-vusb1v8GMregulator-vusb3v1ti,twl4030-vusb3v1GMregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@@regulator-vsimti,twl4030-vsimw@-GMgpioti,twl4030-gpioTGMtwl4030-usbti,twl4030-usb `n|GMpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad8  7 Smadcti,twl4030-madcpower1ti,twl4030-power-omap3-evmti,twl4030-power-idlei2c@48072000 ti,omap3-i2cyH 9txrx+i2c2i2c@48060000 ti,omap3-i2cyH=txrx+i2c3tvp5146@5c ti,tvp5146m2y\mailbox@48094000ti,omap3-mailboxmailboxyH @dsp + 6spi@48098000ti,omap2-mcspiyH A+mcspi1A@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0y ti,tsc2046OB@alu@~(  spi@4809a000ti,omap2-mcspiyH B+mcspi2A +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3A tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0+mcspi4AFGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrxS mmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx $+wlcore@2 ti,wl1271y 7Immc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrxmmu@480bd400Kti,omap2-iommuyH mmu_ispXGMmmu@5d000000Kti,omap2-iommuy]mmu_iva hdisabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@ompu ;< ycommontxrxmcbsp1 txrx}fck hdisabledmcbsp@49022000ti,omap3-mcbspyI I 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&timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer5timer@4903a000ti,omap3430-timeryI*timer6timer@4903c000ti,omap3430-timeryI+timer7timer@4903e000ti,omap3430-timeryI,timer8timer@49040000ti,omap3430-timeryI-timer9timer@48086000ti,omap3430-timeryH`.timer10timer@48088000ti,omap3430-timeryH/timer11timer@48304000ti,omap3430-timeryH0@_timer12usbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hs+ohci@48064400ti,ohci-omap3yHD Lehci@48064800 ti,ehci-omapyHH Mgpmc@6e000000ti,omap3430-gpmcgpmcynrxtx+ethernet@gpmcsmsc,lan9221smsc,lan9115 &@N`r(--x,KCK]u  yusb_otg_hs@480ab000ti,omap3-musbyH \]ymcdma usb_otg_hs "* /usb2-phy92dss@48050000 ti,omap3-dssyHhok dss_core}fck+dispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H oprotophypll hdisabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH hdisabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  hdisabled 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removablecap-power-off-cardref-clock-frequency#iommu-cellsti,#tlb-entriesstatusreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellslabelgpioslinux,default-triggerstartup-delay-usenable-active-highvin-supplydefault-onenable-active-lowpower-supplyenable-gpiosreset-gpiosmode-gpios