78( P'ti,omap3-evm-37xxti,omap3630ti,omap3 +7TI OMAP37XX EVM (TMDSEVM3730)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/ocp@68000000/serial@49042000 l/displaycpus+cpu@0arm,cortex-a8ucpucpus 'O 57pmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+2OUpinmux_twl4030_pins]AOUpinmux_dss_dpi_pins2]OUpinmux_mmc1_pinsP] "$&OUpinmux_mmc2_pins0](*,.02OUpinmux_uart3_pins]nApOUpinmux_wl12xx_gpio]PNOUpinmux_smsc911x_pins]OUscm_conf@270sysconsimple-busp0+ p0OUpbias_regulator@2b0ti,pbias-omap3ti,pbias-omapqpbias_mmc_omap2430xpbias_mmc_omap2430w@-OUclocks+mcbsp5_mux_fck@68ti,composite-mux-clockhOUmcbsp5_fckti,composite-clockOUmcbsp1_mux_fck@4ti,composite-mux-clockO U mcbsp1_fckti,composite-clock OUmcbsp2_mux_fck@4ti,composite-mux-clock O U mcbsp2_fckti,composite-clock OUmcbsp3_mux_fck@68ti,composite-mux-clock hOUmcbsp3_fckti,composite-clockOUmcbsp4_mux_fck@68ti,composite-mux-clock hOUmcbsp4_fckti,composite-clockOUclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+2pinmux_twl4030_vpins ]OUpinmux_dss_dpi_pins10]  OUaes@480c5000 ti,omap3-aesaesH PPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockYOUosc_sys_ck@d40 ti,mux-clock @OUsys_ck@1270ti,divider-clockpOUsys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clockOUdpll4_x2_ckfixed-factor-clockcorex2_fckfixed-factor-clockOUwkup_l4_ickfixed-factor-clockONUNcorex2_d3_fckfixed-factor-clockOUcorex2_d5_fckfixed-factor-clockOUclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockO@U@virt_12m_ck fixed-clockOUvirt_13m_ck fixed-clock]@OUvirt_19200000_ck fixed-clock$OUvirt_26000000_ck fixed-clockOUvirt_38_4m_ck fixed-clockIOUdpll4_ck@d00ti,omap3-dpll-per-j-type-clock D 0OUdpll4_m2_ck@d48ti,divider-clock? HO U dpll4_m2x2_mul_ckfixed-factor-clock O!U!dpll4_m2x2_ck@d00ti,hsdiv-gate-clock! 'O"U"omap_96m_alwon_fckfixed-factor-clock"O)U)dpll3_ck@d00ti,omap3-dpll-core-clock @ 0OUdpll3_m3_ck@1140ti,divider-clock@O#U#dpll3_m3x2_mul_ckfixed-factor-clock#O$U$dpll3_m3x2_ck@d00ti,hsdiv-gate-clock$  'O%U%emu_core_alwon_ckfixed-factor-clock%ObUbsys_altclk fixed-clockO.U.mcbsp_clks fixed-clockOUdpll3_m2_ck@d40ti,divider-clock @OUcore_ckfixed-factor-clockO&U&dpll1_fck@940ti,divider-clock& @O'U'dpll1_ck@904ti,omap3-dpll-clock'  $ @ 4OUdpll1_x2_ckfixed-factor-clockO(U(dpll1_x2m2_ck@944ti,divider-clock( DO<U<cm_96m_fckfixed-factor-clock)O*U*omap_96m_fck@d40 ti,mux-clock* @OEUEdpll4_m3_ck@e40ti,divider-clock @O+U+dpll4_m3x2_mul_ckfixed-factor-clock+O,U,dpll4_m3x2_ck@d00ti,hsdiv-gate-clock, 'O-U-omap_54m_fck@d40 ti,mux-clock-. @O8U8cm_96m_d2_fckfixed-factor-clock*O/U/omap_48m_fck@d40 ti,mux-clock/. @O0U0omap_12m_fckfixed-factor-clock0OGUGdpll4_m4_ck@e40ti,divider-clock @O1U1dpll4_m4x2_mul_ckti,fixed-factor-clock1=KXO2U2dpll4_m4x2_ck@d00ti,gate-clock2 'XOUdpll4_m5_ck@f40ti,divider-clock?@O3U3dpll4_m5x2_mul_ckti,fixed-factor-clock3=KXO4U4dpll4_m5x2_ck@d00ti,hsdiv-gate-clock4 'XOjUjdpll4_m6_ck@1140ti,divider-clock?@O5U5dpll4_m6x2_mul_ckfixed-factor-clock5O6U6dpll4_m6x2_ck@d00ti,hsdiv-gate-clock6 'O7U7emu_per_alwon_ckfixed-factor-clock7OcUcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock& pO9U9clkout2_src_mux_ck@d70ti,composite-mux-clock&*8 pO:U:clkout2_src_ckti,composite-clock9:O;U;sys_clkout2@d70ti,divider-clock;@ pkmpu_ckfixed-factor-clock<O=U=arm_fck@924ti,divider-clock= $emu_mpu_alwon_ckfixed-factor-clock=OdUdl3_ick@a40ti,divider-clock& @O>U>l4_ick@a40ti,divider-clock> @O?U?rm_ick@c40ti,divider-clock? @gpt10_gate_fck@a00ti,composite-gate-clock  OAUAgpt10_mux_fck@a40ti,composite-mux-clock@ @OBUBgpt10_fckti,composite-clockABgpt11_gate_fck@a00ti,composite-gate-clock  OCUCgpt11_mux_fck@a40ti,composite-mux-clock@ @ODUDgpt11_fckti,composite-clockCDcore_96m_fckfixed-factor-clockEOUmmchs2_fck@a00ti,wait-gate-clock OUmmchs1_fck@a00ti,wait-gate-clock OUi2c3_fck@a00ti,wait-gate-clock OUi2c2_fck@a00ti,wait-gate-clock OUi2c1_fck@a00ti,wait-gate-clock OUmcbsp5_gate_fck@a00ti,composite-gate-clock  OUmcbsp1_gate_fck@a00ti,composite-gate-clock  O U core_48m_fckfixed-factor-clock0OFUFmcspi4_fck@a00ti,wait-gate-clockF OUmcspi3_fck@a00ti,wait-gate-clockF OUmcspi2_fck@a00ti,wait-gate-clockF OUmcspi1_fck@a00ti,wait-gate-clockF OUuart2_fck@a00ti,wait-gate-clockF OUuart1_fck@a00ti,wait-gate-clockF  OUcore_12m_fckfixed-factor-clockGOHUHhdq_fck@a00ti,wait-gate-clockH OUcore_l3_ickfixed-factor-clock>OIUIsdrc_ick@a10ti,wait-gate-clockI OUgpmc_fckfixed-factor-clockIcore_l4_ickfixed-factor-clock?OJUJmmchs2_ick@a10ti,omap3-interface-clockJ OUmmchs1_ick@a10ti,omap3-interface-clockJ OUhdq_ick@a10ti,omap3-interface-clockJ OUmcspi4_ick@a10ti,omap3-interface-clockJ OUmcspi3_ick@a10ti,omap3-interface-clockJ OUmcspi2_ick@a10ti,omap3-interface-clockJ OUmcspi1_ick@a10ti,omap3-interface-clockJ OUi2c3_ick@a10ti,omap3-interface-clockJ OUi2c2_ick@a10ti,omap3-interface-clockJ OUi2c1_ick@a10ti,omap3-interface-clockJ OUuart2_ick@a10ti,omap3-interface-clockJ OUuart1_ick@a10ti,omap3-interface-clockJ  OUgpt11_ick@a10ti,omap3-interface-clockJ  OUgpt10_ick@a10ti,omap3-interface-clockJ  OUmcbsp5_ick@a10ti,omap3-interface-clockJ  OUmcbsp1_ick@a10ti,omap3-interface-clockJ  OUomapctrl_ick@a10ti,omap3-interface-clockJ OUdss_tv_fck@e00ti,gate-clock8OUdss_96m_fck@e00ti,gate-clockEOUdss2_alwon_fck@e00ti,gate-clockOUdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock OKUKgpt1_mux_fck@c40ti,composite-mux-clock@ @OLULgpt1_fckti,composite-clockKLaes2_ick@a10ti,omap3-interface-clockJ OUwkup_32k_fckfixed-factor-clock@OMUMgpio1_dbck@c00ti,gate-clockM OUsha12_ick@a10ti,omap3-interface-clockJ OUwdt2_fck@c00ti,wait-gate-clockM OUwdt2_ick@c10ti,omap3-interface-clockN OUwdt1_ick@c10ti,omap3-interface-clockN OUgpio1_ick@c10ti,omap3-interface-clockN OUomap_32ksync_ick@c10ti,omap3-interface-clockN OUgpt12_ick@c10ti,omap3-interface-clockN OUgpt1_ick@c10ti,omap3-interface-clockN OUper_96m_fckfixed-factor-clock)O U per_48m_fckfixed-factor-clock0OOUOuart3_fck@1000ti,wait-gate-clockO OUgpt2_gate_fck@1000ti,composite-gate-clockOPUPgpt2_mux_fck@1040ti,composite-mux-clock@@OQUQgpt2_fckti,composite-clockPQgpt3_gate_fck@1000ti,composite-gate-clockORURgpt3_mux_fck@1040ti,composite-mux-clock@@OSUSgpt3_fckti,composite-clockRSgpt4_gate_fck@1000ti,composite-gate-clockOTUTgpt4_mux_fck@1040ti,composite-mux-clock@@OUUUgpt4_fckti,composite-clockTUgpt5_gate_fck@1000ti,composite-gate-clockOVUVgpt5_mux_fck@1040ti,composite-mux-clock@@OWUWgpt5_fckti,composite-clockVWgpt6_gate_fck@1000ti,composite-gate-clockOXUXgpt6_mux_fck@1040ti,composite-mux-clock@@OYUYgpt6_fckti,composite-clockXYgpt7_gate_fck@1000ti,composite-gate-clockOZUZgpt7_mux_fck@1040ti,composite-mux-clock@@O[U[gpt7_fckti,composite-clockZ[gpt8_gate_fck@1000ti,composite-gate-clock O\U\gpt8_mux_fck@1040ti,composite-mux-clock@@O]U]gpt8_fckti,composite-clock\]gpt9_gate_fck@1000ti,composite-gate-clock O^U^gpt9_mux_fck@1040ti,composite-mux-clock@@O_U_gpt9_fckti,composite-clock^_per_32k_alwon_fckfixed-factor-clock@O`U`gpio6_dbck@1000ti,gate-clock`OUgpio5_dbck@1000ti,gate-clock`OUgpio4_dbck@1000ti,gate-clock`OUgpio3_dbck@1000ti,gate-clock`OUgpio2_dbck@1000ti,gate-clock` OUwdt3_fck@1000ti,wait-gate-clock` OUper_l4_ickfixed-factor-clock?OaUagpio6_ick@1010ti,omap3-interface-clockaOUgpio5_ick@1010ti,omap3-interface-clockaOUgpio4_ick@1010ti,omap3-interface-clockaOUgpio3_ick@1010ti,omap3-interface-clockaOUgpio2_ick@1010ti,omap3-interface-clocka OUwdt3_ick@1010ti,omap3-interface-clocka OUuart3_ick@1010ti,omap3-interface-clocka OUuart4_ick@1010ti,omap3-interface-clockaOUgpt9_ick@1010ti,omap3-interface-clocka OUgpt8_ick@1010ti,omap3-interface-clocka OUgpt7_ick@1010ti,omap3-interface-clockaOUgpt6_ick@1010ti,omap3-interface-clockaOUgpt5_ick@1010ti,omap3-interface-clockaOUgpt4_ick@1010ti,omap3-interface-clockaOUgpt3_ick@1010ti,omap3-interface-clockaOUgpt2_ick@1010ti,omap3-interface-clockaOUmcbsp2_ick@1010ti,omap3-interface-clockaOUmcbsp3_ick@1010ti,omap3-interface-clockaOUmcbsp4_ick@1010ti,omap3-interface-clockaOUmcbsp2_gate_fck@1000ti,composite-gate-clockO U mcbsp3_gate_fck@1000ti,composite-gate-clockOUmcbsp4_gate_fck@1000ti,composite-gate-clockOUemu_src_mux_ck@1140 ti,mux-clockbcd@OeUeemu_src_ckti,clkdm-gate-clockeOfUfpclk_fck@1140ti,divider-clockf@pclkx2_fck@1140ti,divider-clockf@atclk_fck@1140ti,divider-clockf@traceclk_src_fck@1140 ti,mux-clockbcd@OgUgtraceclk_fck@1140ti,divider-clockg @secure_32k_fck fixed-clockOhUhgpt12_fckfixed-factor-clockhwdt1_fckfixed-factor-clockhsecurity_l4_ick2fixed-factor-clock?OiUiaes1_ick@a14ti,omap3-interface-clocki rng_ick@a14ti,omap3-interface-clocki sha11_ick@a14ti,omap3-interface-clocki des1_ick@a14ti,omap3-interface-clocki cam_mclk@f00ti,gate-clockjXcam_ick@f10!ti,omap3-no-wait-interface-clock?OUcsi2_96m_fck@f00ti,gate-clockOUsecurity_l3_ickfixed-factor-clock>OkUkpka_ick@a14ti,omap3-interface-clockk icr_ick@a10ti,omap3-interface-clockJ des2_ick@a10ti,omap3-interface-clockJ mspro_ick@a10ti,omap3-interface-clockJ mailboxes_ick@a10ti,omap3-interface-clockJ ssi_l4_ickfixed-factor-clock?OrUrsr1_fck@c00ti,wait-gate-clock sr2_fck@c00ti,wait-gate-clock sr_l4_ickfixed-factor-clock?dpll2_fck@40ti,divider-clock&@OlUldpll2_ck@4ti,omap3-dpll-clockl$@4OmUmdpll2_m2_ck@44ti,divider-clockmDOnUniva2_ck@0ti,wait-gate-clocknOUmodem_fck@a00ti,omap3-interface-clock OUsad2d_ick@a10ti,omap3-interface-clock> OUmad2d_ick@a18ti,omap3-interface-clock> OUmspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock OoUossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock @$OpUpssi_ssr_fck_3430es2ti,composite-clockopOqUqssi_sst_fck_3430es2fixed-factor-clockqOUhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockI OUssi_ick_3430es2@a10ti,omap3-ssi-interface-clockr OUusim_gate_fck@c00ti,composite-gate-clockE  O}U}sys_d2_ckfixed-factor-clockOtUtomap_96m_d2_fckfixed-factor-clockEOuUuomap_96m_d4_fckfixed-factor-clockEOvUvomap_96m_d8_fckfixed-factor-clockEOwUwomap_96m_d10_fckfixed-factor-clockE OxUxdpll5_m2_d4_ckfixed-factor-clocksOyUydpll5_m2_d8_ckfixed-factor-clocksOzUzdpll5_m2_d16_ckfixed-factor-clocksO{U{dpll5_m2_d20_ckfixed-factor-clocksO|U|usim_mux_fck@c40ti,composite-mux-clock(tuvwxyz{| @O~U~usim_fckti,composite-clock}~usim_ick@c10ti,omap3-interface-clockN  OUdpll5_ck@d04ti,omap3-dpll-clock  $ L 4OUdpll5_m2_ck@d50ti,divider-clock POsUssgx_gate_fck@b00ti,composite-gate-clock& OUcore_d3_ckfixed-factor-clock&OUcore_d4_ckfixed-factor-clock&OUcore_d6_ckfixed-factor-clock&OUomap_192m_alwon_fckfixed-factor-clock"OUcore_d2_ckfixed-factor-clock&OUsgx_mux_fck@b40ti,composite-mux-clock * @OUsgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clock> OUcpefuse_fck@a08ti,gate-clock OUts_fck@a08ti,gate-clock@ OUusbtll_fck@a08ti,wait-gate-clocks OUusbtll_ick@a18ti,omap3-interface-clockJ OUmmchs3_ick@a10ti,omap3-interface-clockJ OUmmchs3_fck@a00ti,wait-gate-clock OUdss1_alwon_fck_3430es2@e00ti,dss-gate-clockXOUdss_ick_3430es2@e10ti,omap3-dss-interface-clock?OUusbhost_120m_fck@1400ti,gate-clocksOUusbhost_48m_fck@1400ti,dss-gate-clock0OUusbhost_ick@1410ti,omap3-dss-interface-clock?OUuart4_fck@1000ti,wait-gate-clockOOUclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomainfdpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainmd2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain counter@48320000ti,omap-counter32kH2  counter_32kinterrupt-controller@48200000ti,omap3-intcH OUdma-controller@48056000"ti,omap3630-sdmati,omap3430-sdmaH`  `OUgpio@48310000ti,omap3-gpioH1gpio1OUgpio@49050000ti,omap3-gpioIgpio2gpio@49052000ti,omap3-gpioI gpio3gpio@49054000ti,omap3-gpioI@ gpio4gpio@49056000ti,omap3-gpioI`!gpio5OUgpio@49058000ti,omap3-gpioI"gpio6OUserial@4806a000ti,omap3-uartH HR12txrxuart1lserial@4806c000ti,omap3-uartHIJ34txrxuart2lserial@49020000ti,omap3-uartIJn56txrxuart3l"default0i2c@48070000 ti,omap3-i2cH8txrx+i2c1'@twl@48H  ti,twl4030"default0rtcti,twl4030-rtc bciti,twl4030-bci :watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' OUregulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0OUregulator-vmmc2ti,twl4030-vmmc2:0OUregulator-vusb1v5ti,twl4030-vusb1v5OUregulator-vusb1v8ti,twl4030-vusb1v8OUregulator-vusb3v1ti,twl4030-vusb3v1OUregulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@Hregulator-vsimti,twl4030-vsimw@-OUgpioti,twl4030-gpio\OUtwl4030-usbti,twl4030-usb hvOUpwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad8  7 Smadcti,twl4030-madcpower1ti,twl4030-power-omap3-evmti,twl4030-power-idlei2c@48072000 ti,omap3-i2cH 9txrx+i2c2i2c@48060000 ti,omap3-i2cH=txrx+i2c3tvp5146@5c ti,tvp5146m2\mailbox@48094000ti,omap3-mailboxmailboxH @!dsp 3 >spi@48098000ti,omap2-mcspiH A+mcspi1I@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3tsc2046@0 ti,tsc2046WB@it}@(  spi@4809a000ti,omap2-mcspiH B+mcspi2I +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3I tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4IFGtx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>txrxS"default0mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx,+"default0wlcore@2 ti,wl1271 ?Immc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx Sdisabledmmu@480bd400Zti,omap2-iommuH mmu_ispgOUmmu@5d000000Zti,omap2-iommu]mmu_iva Sdisabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@wmpu ;< commontxrxmcbsp1 txrxfck Sdisabledmcbsp@49022000ti,omap3-mcbspI I wmpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrxfckick Sdisabledmcbsp@49024000ti,omap3-mcbspI@I wmpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrxfckick Sdisabledmcbsp@49026000ti,omap3-mcbspI`wmpu 67 commontxrxmcbsp4txrxfck Sdisabledmcbsp@48096000ti,omap3-mcbspH `wmpu QR commontxrxmcbsp5txrxfck Sdisabledsham@480c3000ti,omap3-shamshamH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivaH timer@48318000ti,omap3430-timerH1%timer1timer@49032000ti,omap3430-timerI &timer2timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11timer@48304000ti,omap3430-timerH0@_timer12usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ohci@48064400ti,ohci-omap3HD Lehci@48064800 ti,ehci-omapHH Mgpmc@6e000000ti,omap3430-gpmcgpmcnrxtx+ 0,OUethernet@gpmcsmsc,lan9221smsc,lan9115.HVhz(-- x4KKKe}  "default0nand@0,0ti,omap2-nand  hynix,h8kds0un0mer-4embch8-HV,h,z",(6 @RR(+partition@0 >X-Loaderpartition@0x80000>U-Bootpartition@0x1c0000 >Environment$partition@0x280000>Kernel(Ppartition@0x780000 >Filesystemxusb_otg_hs@480ab000ti,omap3-musbH \]mcdma usb_otg_hsDOW `ow |usb2-phy2dss@48050000 ti,omap3-dssHSok dss_corefck+"default0dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H wprotophypll Sdisabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH Sdisabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  Sdisabled dss_vencfcktv_dac_clkportendpointOUssi-controller@48058000 ti,omap3-ssissiSokHHwsysgddGgdd_mpu+ q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHwtxrx CDssi-port@4805b000ti,omap3-ssi-portHHwtxrx EFserial@49042000ti,omap3-uartI PQRtxrxuart4lregulator-abb-mpu ti,abb-v1 xabb_mpu_iva+H0rH0hwbase-addressint-address`sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\+2isp@480bc000 ti,omap3-ispH H qports+bandgap@48002524H%$ti,omap36xx-bandgap regulator-vddvarioregulator-fixed xvddvarioHOUregulator-vdd33aregulator-fixedxvdd33aHOUleds gpio-ledsledb>omap3evm::ledb  default-onwl12xx_vmmcregulator-fixedxvwl1271w@w@  2p C V"default0OUbacklightgpio-backlight a regulator-lcd-3v3regulator-fixedxlcd_3v32Z2Z 2p  lOUdisplaysharp,ls037v7dw01>lcd ~  $ portendpointOUmemory@80000000umemory compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-masklinux,phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0bci3v1-supplyregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthnon-removablecap-power-off-cardref-clock-frequencystatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phyphysphy-namespowerremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsgpioslinux,default-triggerstartup-delay-usenable-active-highvin-supplydefault-onenable-active-lowpower-supplyenable-gpiosreset-gpiosmode-gpios