8$(*chipspark,popmetal-rk3288rockchip,rk3288&7PopMetal-RK3288chosenaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/dwmmc@ff0f0000k/dwmmc@ff0c0000q/dwmmc@ff0d0000w/dwmmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000memorymemoryarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12`@p@ @OOa sB@ ~ ' 9  K 0 $@29EKcpu@501cpuarm,cortex-a12EKcpu@502cpuarm,cortex-a12EKcpu@503cpuarm,cortex-a12EKamba simple-busSdma-controller@ff250000arm,pl330arm,primecell%@Ze2 apb_pclkEKdma-controller@ff600000arm,pl330arm,primecell`@Ze2 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@Ze2 apb_pclkEMKMreserved-memorySdma-unusable@fe000000oscillator fixed-clockn6xin24mE K timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 2 a timerpclkdisplay-subsystemrockchip,display-subsystem dwmmc@ff0c0000rockchip,rk3288-dw-mshcр 2Drvbiuciuciu-driveciu-sample  @okay '8JU_defaultm wdwmmc@ff0d0000rockchip,rk3288-dw-mshcр 2Eswbiuciuciu-driveciu-sample ! @ disableddwmmc@ff0e0000rockchip,rk3288-dw-mshcр 2Ftxbiuciuciu-driveciu-sample "@ disableddwmmc@ff0f0000rockchip,rk3288-dw-mshcр 2Guybiuciuciu-driveciu-sample #@okay JU_defaultmwsaradc@ff100000rockchip,saradc $2I[saradcapb_pclkW saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi2ARspiclkapb_pclk  txrx ,_defaultm disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi2BSspiclkapb_pclk txrx -_defaultm  disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi2CTspiclkapb_pclktxrx ._defaultm!"#$ disabledi2c@ff140000rockchip,rk3288-i2c >i2c2M_defaultm%okayak8963@0dasahi-kasei,ak8975 &&_defaultm'l3g4200d@68st,l3g4200d-gyrokmma8452@1d fsl,mma8452&&_defaultm(i2c@ff150000rockchip,rk3288-i2c ?i2c2O_defaultm)okayi2c@ff160000rockchip,rk3288-i2c @i2c2P_defaultm*okayi2c@ff170000rockchip,rk3288-i2c Ai2c2Q_defaultm+okayE^K^serial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 72MUbaudclkapb_pclk_defaultm,okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 82NVbaudclkapb_pclk_defaultm-okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 92OWbaudclkapb_pclk_defaultm.okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :2PXbaudclkapb_pclk_defaultm/okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;2QYbaudclkapb_pclk_defaultm0okaythermal-zonesreserve_thermal1cpu_thermald1tripscpu_alert0&p2passiveE2K2cpu_alert1&$2passiveE3K3cpu_crit&_2 criticalcooling-mapsmap0=2 Bmap1=3 Bgpu_thermald1tripsgpu_alert0&p2passiveE4K4gpu_crit&_2 criticalcooling-mapsmap0=4 Btsadc@ff280000rockchip,rk3288-tsadc( %2HZtsadcapb_pclk tsadc-apb_initdefaultsleepm5Q6[5e{sokayE1K1ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq782fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB stmmacethok8rgmiiinput 9 ('B@=M:_defaultm;d0musb@ff500000 generic-ehciP 2usbhostv<{usb disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 2otghostv= {usb2-phy disabledusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 2otgotg@@ v> {usb2-phy disabledusb@ff5c0000 generic-ehci\ 2usbhost disabledi2c@ff650000rockchip,rk3288-i2ce <i2c2L_defaultm?okaypmic@1brockchip,rk808&@_defaultmABxin32krk808-clkout2CCCC&C2C>DJVcCp}regulatorsDCDC_REG1 qpvdd_armEKregulator-state-memDCDC_REG2 Pvdd_gpuregulator-state-mem B@DCDC_REG3vcc_ddrregulator-state-memDCDC_REG42Z2Zvcc_ioEKregulator-state-mem 2ZLDO_REG12Z2Zvcc_lanE8K8regulator-state-mem 2ZLDO_REG22Z2Z vccio_sdEKregulator-state-memLDO_REG3B@B@vdd_10regulator-state-mem B@LDO_REG4w@w@ vcc18_lcdregulator-state-mem w@LDO_REG5w@2Zldo5LDO_REG6B@B@ vdd10_lcdregulator-state-mem B@LDO_REG7w@w@vcc_18EDKDregulator-state-mem w@LDO_REG82Z2Zvcca_33EJKJregulator-state-mem 2ZSWITCH_REG1 vccio_wlELKLregulator-state-memSWITCH_REG2vcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c2N_defaultmEokaypwm@ff680000rockchip,rk3288-pwmh<_defaultmF2^pwm disabledpwm@ff680010rockchip,rk3288-pwmh<_defaultmG2^pwm disabledpwm@ff680020rockchip,rk3288-pwmh <_defaultmH2^pwm disabledpwm@ff680030rockchip,rk3288-pwmh0<_defaultmI2^pwm disabledbus_intmem@ff700000 mmio-sramp Spsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsEKpower-controller!rockchip,rk3288-power-controllerG=hM EPKPpd_vio@9 2chgfdehilkjpd_hevc@11 2oppd_video@12 2pd_gpu@13 2syscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv7[H=jk$h#gׄeрxhрxhEKsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwE7K7edp-phyrockchip,rk3288-dp-phy2h24m} disabledE[K[io-domains"rockchip,rk3288-io-voltage-domainokayJK8Lwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt2p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif  hclkmclk2TMtx 6_defaultmN7 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 5MMtxrxi2s_hclki2s_clk2R_defaultmO6 disabledcypto-controller@ff8a0000rockchip,rk3288-crypto@ 0 2}aclkhclksclkapb_pclk crypto-rstokayvop@ff930000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vopPP def axiahbdclk^QokayportE K endpoint@0eRE_K_endpoint@1eSE\K\endpoint@2eTEYKYiommu@ff930300rockchip,iommu  vopb_mmuPP uokayEQKQvop@ff940000rockchip,rk3288-vop 2aclk_vopdclk_vophclk_vopPP  axiahbdclk^UokayportE K endpoint@0eVE`K`endpoint@1eWE]K]endpoint@2eXEZKZiommu@ff940300rockchip,iommu  vopl_mmuPP uokayEUKUmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 2~d refpclkPP 7 disabledportsportendpoint@0eYETKTendpoint@1eZEXKXdp@ff970000rockchip,rk3288-dp@ b2icdppclkv[{dpodp7 disabledportsport@0endpoint@0e\ESKSendpoint@1e]EWKWhdmi@ff980000rockchip,rk3288-dw-hdmi7 g2hm iahbisfrPP okay^portsportendpoint@0e_ERKRendpoint@1e`EVKVinterrupt-controller@ffc01000 arm,gic-400  @ `   EKefuse@ffb40000rockchip,rockchip-efuse 2q pclk_efusecpu_leakage@17phyrockchip,rk3288-usb-phy7okayusb-phy@320} 2]phyclkE>K>usb-phy@334}42^phyclkE<K<usb-phy@348}H2_phyclkE=K=pinctrlrockchip,rk3288-pinctrl7Sgpio0@ff750000rockchip,gpio-banku Q2@E@K@gpio1@ff780000rockchip,gpio-bankx R2Agpio2@ff790000rockchip,gpio-banky S2Bgpio3@ff7a0000rockchip,gpio-bankz T2Cgpio4@ff7b0000rockchip,gpio-bank{ U2DE9K9gpio5@ff7c0000rockchip,gpio-bank| V2Egpio6@ff7d0000rockchip,gpio-bank} W2Fgpio7@ff7e0000rockchip,gpio-bank~ X2GEgKggpio8@ff7f0000rockchip,gpio-bank Y2HE&K&hdmihdmi-ddc aapcfg-pull-upEbKbpcfg-pull-downEcKcpcfg-pull-noneEaKapcfg-pull-none-12ma EdKdsleepglobal-pwroffaEBKBddrio-pwroffaddr0-retentionbddr1-retentionbedpedp-hpd ci2c0i2c0-xfer aaE?K?i2c1i2c1-xfer aaE%K%i2c2i2c2-xfer  a aEEKEi2c3i2c3-xfer aaE)K)i2c4i2c4-xfer aaE*K*i2c5i2c5-xfer aaE+K+i2s0i2s0-bus`aaaaaaEOKOsdmmcsdmmc-clkaE K sdmmc-cmdbE K sdmmc-cdbEKsdmmc-bus1bsdmmc-bus4@bbbbEKsdmmc-pwr aEhKhsdio0sdio0-bus1bsdio0-bus4@bbbbsdio0-cmdbsdio0-clkasdio0-cdbsdio0-wpbsdio0-pwrbsdio0-bkpwrbsdio0-intbsdio1sdio1-bus1bsdio1-bus4@bbbbsdio1-cdbsdio1-wpbsdio1-bkpwrbsdio1-intbsdio1-cmdbsdio1-clkasdio1-pwr bemmcemmc-clkaEKemmc-cmdbEKemmc-pwr bEKemmc-bus1bemmc-bus4@bbbbemmc-bus8bbbbbbbbEKspi0spi0-clk bEKspi0-cs0 bEKspi0-txbEKspi0-rxbEKspi0-cs1bspi1spi1-clk bEKspi1-cs0 bE K spi1-rxbEKspi1-txbEKspi2spi2-cs1bspi2-clkbE!K!spi2-cs0bE$K$spi2-rxbE#K#spi2-tx bE"K"uart0uart0-xfer baE,K,uart0-ctsbuart0-rtsauart1uart1-xfer b aE-K-uart1-cts buart1-rts auart2uart2-xfer baE.K.uart3uart3-xfer baE/K/uart3-cts buart3-rts auart4uart4-xfer  b aE0K0uart4-ctsbuart4-rtsatsadcotp-gpio aE5K5otp-out aE6K6pwm0pwm0-pinaEFKFpwm1pwm1-pinaEGKGpwm2pwm2-pinaEHKHpwm3pwm3-pinaEIKIgmacrgmii-pinsaaaaddddaaa ddaaE;K;rmii-pinsaaaaaaaaaaspdifspdif-tx aENKNak8963comp-intbE'K'buttonspwrbtnbEeKedvpdvp-pwraEjKjirir-intbEfKfmma8452gsensor-intbE(K(pmicpmic-intbEAKAexternal-gmac-clock fixed-clocksY@ ext_gmacE:K:gpio-keys gpio-keys_defaultmepower !@'t2GPIO Key Power8Idir-receivergpio-ir-receiver !@_defaultmfflash-regulatorregulator-fixed vcc_flashw@w@[EKsdmmc-regulatorregulator-fixed  g _defaultmhvcc_sd2Z2Zf[EKvsys-regulatorregulator-fixedvcc_sysLK@LK@ECKCvcc18-dvp-regulatorregulator-fixed vcc18-dvpw@w@[iEKKKvcc28-dvp-regulatorregulator-fixedw  @_defaultmj vcc28_dvp**[EiKi #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2device_typereginterruptsinterrupt-affinityenable-methodrockchip,pmuresetsoperating-points#cooling-cellsclock-latencyclockscpu0-supplylinux,phandleranges#dma-cellsarm,pl330-broken-no-flushpclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredportsclock-freq-min-maxfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wpnum-slotspinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsreset-namesdmasdma-namesst,drdy-int-pinreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeg-use-dmarockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cells#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channelspower-domainsiommusremote-endpoint#iommu-cellsddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsbias-pull-upbias-pull-downbias-disabledrive-strengthautorepeatgpioslinux,codelabellinux,input-typedebounce-intervalvin-supplystartup-delay-usenable-active-high