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#address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2serial3serial4serial5ethernet0ethernet1spi0device_typeregclocksclock-namesoperating-points-v2ti,syscon-efuseti,syscon-revclock-latencycpu0-supplylinux,phandleopp-hzopp-microvoltopp-supported-hwopp-suspendinterrupt-controller#interrupt-cellsinterruptscache-unifiedcache-levelrangesti,hwmodsreg-namesti,pm-firmware#clock-cellsclock-frequencyti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitclock-multclock-divti,set-rate-parentti,bit-shiftti,dividersti,clock-multti,clock-divti,index-power-of-twopinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinsti,rprocmboxes#dma-cellsdma-requestsdma-mastersinterrupt-namesti,tptcsti,edma-memcpy-channelsstatus#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-send-noirqti,mbox-txti,mbox-rxti,timer-alwonti,timer-pwmgpio-controller#gpio-cells#hwlock-cellspinctrl-namespinctrl-0pinctrl-1pagesizeregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onti,vsel0-state-highti,vsel1-state-highvin-supplyti,dual-voltti,needs-special-resetdmasdma-namesvmmc-supplybus-widthcd-gpiosassigned-clocksassigned-clock-ratescpdma_channelsale_entriesbd_ram_sizeno_bd_rammac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftsysconbus_freqmac-addressphy_idphy-mode#pwm-cells#io-channel-cellsgpmc,num-csgpmc,num-waitpinssyscon-phy-power#phy-cellsutmi-modephysphy-namesmaximum-speeddr_modesnps,dis_u3_susphy_quirksnps,dis_u2_susphy_quirkspi-max-frequencyspi-cpolspi-cphaspi-tx-bus-widthspi-rx-bus-widthlabelsyscon-raminitlinux,code