8 (#adapteva,parallellaxlnx,zynq-7000&Adapteva Parallella Boardchosen<,earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait5serial0:115200n8aliasesA/amba/ethernet@e000b000K/amba/serial@e0001000memorySmemory_@cpuscpu@0arm,cortex-a9Scpu_cjx ,+B@B@cpu@1arm,cortex-a9Scpu_cpmuarm,cortex-a9-pmu_0fixedregulator@0regulator-fixedVCCPINTB@B@amba simple-bus$adc@f8007100xlnx,zynq-xadc-1.00.a_q  c can@e0008000xlnx,zynq-can-1.0 +disabledc$ 2can_clkpclk_ >@L@can@e0009000xlnx,zynq-can-1.0 +disabledc% 2can_clkpclk_ 3>@L@gpio@e000a000xlnx,zynq-gpio-1.0Zc*fv _i2c@e0004000cdns,i2c-r1p10+okayc& _@isl9305@68 isil,isl9305_hregulatorsdcd1VDD_DSPdcd21P35Vldo1VDD_ADJldo2 VDD_GPIOi2c@e0005000cdns,i2c-r1p10 +disabledc' 0_Pinterrupt-controller@f8f01000arm,cortex-a9-gicv_cache-controller@f8f02000arm,pl310-cache_    memory-controller@f8006000xlnx,zynq-ddrc-a05_`serial@e0000000xlnx,xuartpscdns,uart-r1p8 +disabledc(2uart_clkpclk_ serial@e0001000xlnx,xuartpscdns,uart-r1p8+okayc)2uart_clkpclk_ 2spi@e0006000xlnx,zynq-spi-r1p6_` +disabled c" 2ref_clkpclkspi@e0007000xlnx,zynq-spi-r1p6_p +disabled 1c# 2ref_clkpclkethernet@e000b000cdns,zynq-gemcdns,gem_+okay c 2pclkhclktx_clk rgmii-idethernet-phy@04ethernet-phy-id0141.0e90ethernet-phy-ieee802.3-c22_  ethernet@e000c000cdns,zynq-gemcdns,gem_ +disabled -c2pclkhclktx_clksdhci@e0100000arasan,sdhci-8.9a +disabled2clk_xinclk_ahbc  _sdhci@e0101000arasan,sdhci-8.9a+okay2clk_xinclk_ahbc! /_slcr@f8000000!xlnx,zynq-slcrsysconsimple-mfd_$clkc@100xlnx,ps7-clkc jarmpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apb_(Urstc@200xlnx,zynq-reset_H9Fpinctrl@700xlnx,pinctrl-zynq_Fdmac@f8003000arm,pl330arm,primecell_0.Mabortdma0dma1dma2dma3dma4dma5dma6dma7l ()*+]hvc 2apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.0_p c 2ref_clkFtimer@f8f00200arm,cortex-a9-global-timer_   ctimer@f8001000$    cdns,ttcc_timer@f8002000$%&' cdns,ttcc_ timer@f8f00600  arm,cortex-a9-twd-timer_ cusb@e0002000"xlnx,zynq-usb-2.20achipidea,usb2 +disabledc _ ulpiusb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2 +disabledc ,_0ulpiwatchdog@f8005000c-cdns,wdt-r1p2 _P  #address-cells#size-cellscompatiblemodelbootargsstdout-pathethernet0serial0device_typeregclocksclock-latencycpu0-supplyoperating-pointsinterruptsinterrupt-parentregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onlinux,phandlerangesstatusclock-namestx-fifo-depthrx-fifo-depth#gpio-cellsgpio-controllerinterrupt-controller#interrupt-cellsarm,data-latencyarm,tag-latencycache-unifiedcache-levelphy-modephy-handlemarvell,reg-init#clock-cellsfclk-enableclock-output-namesps-clk-frequency#reset-cellssysconinterrupt-names#dma-cells#dma-channels#dma-requestsphy_typetimeout-sec