^8X,(W*ad,medcom-widead,tamontennvidia,tegra20&!7Avionic Design Medcom-Wide boardchosen=serial0:115200n8aliasesI/i2c@7000d000/tps6586x@34N/rtc@7000e000S/serial@70006300memory[memoryg host1x@50000000!nvidia,tegra20-host1xsimple-busgP@kACv}host1x TTmpe@54040000nvidia,tegra20-mpegT kDv<}<mpevi@54080000nvidia,tegra20-vigT kEvd}viepp@540c0000nvidia,tegra20-eppgT  kFv}eppisp@54100000nvidia,tegra20-ispgT kGv}ispgr2d@54140000nvidia,tegra20-gr2dgT kHv}2dgr3d@54180000nvidia,tegra20-gr3dgTv}3ddc@54200000nvidia,tegra20-dcgT  kIvy dcparent}dcrgbokaydc@54240000nvidia,tegra20-dcgT$ kJvy dcparent}dcrgb disabledhdmi@54280000nvidia,tegra20-hdmigT( kKv3u hdmiparent}3hdmi disabled otvo@542c0000nvidia,tegra20-tvogT, kLvf disableddsi@54300000nvidia,tegra20-dsigT0v0}0dsi disabledtimer@50040600arm,cortex-a9-twd-timer&gP  k vinterrupt-controller@50041000arm,cortex-a9-gicgPP&"(cache-controller@50043000arm,pl310-cachegP0 0 AQ_interrupt-controller@60004000nvidia,tegra20-ictlr g`@`AP`BP`CP&"(timer@60005000nvidia,tegra20-timerg`P`0k)*vclock@60006000nvidia,tegra20-carg``kx"(flow-controller@60007000nvidia,tegra20-flowctrlg`pdma@6000a000nvidia,tegra20-apbdmag`khijklmnopqrstuvwv"}"dma" ( ahb@6000c000nvidia,tegra20-ahbg`gpio@6000d000nvidia,tegra20-gpiog`Tk !"#7WY"(apbmisc@70000800nvidia,tegra20-apbmiscgpdppinmux@70000014nvidia,tegra20-pinmux gpp pphdefault pinmux" ( ataataideatb atbgmagmesdio4atcatcnandatd#atdategmbgmdgpuspiaspibspicgmicdev1cdev1 plla_outcdev2cdev2 pllp_out4crtpcrtpcrtcsuscsusvi_sensor_clkdap1dap1dap1dap2dap2dap2dap3dap3dap3dap4dap4dap4dtadtadtdsdio2dtb dtbdtcdtersvd1dtfdtfi2c3gmcgmcuartdgpu7gpu7rtckgpvgpvslxaslxkpciehdinthdinthdmii2cpi2cpi2cpirrx irrxirtxuartakbcakbcakbcbkbcckbcdkbcekbcfkbclcsnlcsnld0ld1ld2ld3ld4ld5ld6ld7ld8ld9ld10ld11ld12ld13ld14ld15ld16ld17ldcldilhp0lhp1lhp2lhslm0lm1lpplpw0lpw1lpw2lsc0lsc1lscklsdalsdilspilvp0lvp1lvs displayaowcowcspdispdouacrsvd2pmcpmcpwr_onrmrmi2c1sdb sdbsdcsddpwmsdio1sdio1sdio1slxc slxcslxdspdifspidspidspiespifspi1spig spigspih spi2_altuaa uaauabudaulpiuaduadirdaucaucaucbuartcconf_atajataatbatcatdatecdev1cdev2dap1dtbgmagmbgmcgmdgmegpu7gpvi2cpptarmslxaslxkspiaspibuacconf_ck32-ck32ddrcpmcapmcbpmccpmcdpmcexm2cxm2dconf_csuscsusspidspifconf_crtpGcrtpdap2dap3dap4dtcdtedtfgpusdio1slxcslxdspdispdospigudaconf_ddc.ddcdtadtdkbcakbcbkbcckbcdkbcekbcfsdcconf_hdint9hdintlcsnldclm1lpw1lsc1lscklsdalsdilvp0owcsdbconf_irrx1irrxirtxsddspicspiespihuaauabuaducaucbconf_lclclsconf_ld0ld0ld1ld2ld3ld4ld5ld6ld7ld8ld9ld10ld11ld12ld13ld14ld15ld16ld17ldilhp0lhp1lhp2lhslm0lpplpw0lpw2lsc0lspilvp1lvspmcconf_ld17_0ld17_0ld19_18ld21_20ld23_22pinmux_i2cmux_ddc"(ddcddci2c2ptaptarsvd4pinmux_i2cmux_pta"(ddcddcrsvd4ptaptai2c2pinmux_i2cmux_idle"(ddcddcrsvd4ptaptarsvd4das@70000c00nvidia,tegra20-dasgp ac97@70002000nvidia,tegra20-ac97gp  kQv}ac97 rxtx disabledi2s@70002800nvidia,tegra20-i2sgp( k v } i2s  rxtxokay"(i2s@70002a00nvidia,tegra20-i2sgp* kv}i2s  rxtx disabledserial@70006000nvidia,tegra20-uartgp`@  k$v}serial  rxtx disabledserial@70006040nvidia,tegra20-uartgp`@@  k%v`}serial rxtx disabledserial@70006200nvidia,tegra20-uartgpb  k.v7}7serial rxtx disabledserial@70006300nvidia,tegra20-uartgpc  kZvA}Aserial  rxtxokayserial@70006400nvidia,tegra20-uartgpd  k[vB}Bserial  rxtx disabledpwm@7000a000nvidia,tegra20-pwmgpv}pwmokay"(rtc@7000e000nvidia,tegra20-rtcgp kvi2c@7000c000nvidia,tegra20-i2cgp k&v |div-clkfast-clk} i2c  rxtxokay wm8903@1a wlf,wm8903g&k0;dH"(spi@7000c380nvidia,tegra20-sflashgpÀ k'v+}+spi rxtx disabledi2c@7000c400nvidia,tegra20-i2cgp kTv6|div-clkfast-clk}6i2c  rxtxokay "(i2c@7000c500nvidia,tegra20-i2cgp k\vC|div-clkfast-clk}Ci2c  rxtx disabledi2c@7000d000nvidia,tegra20-i2c-dvcgp k5v/|div-clkfast-clk}/i2c  rxtxokay tps6586x@34 ti,tps6586xg4 kVQl w        "(regulatorssysvdd_sys" ( sm0vdd_sys_sm0,vdd_coreO.Osm1vdd_sys_sm1,vdd_cpuB@.B@sm2vdd_sys_sm2,vin_ldo*8u .8u " ( ldo0vdd_ldo0,vddio_pex_clk2Z.2Z"(ldo1vdd_ldo1,avdd_pll*.ldo2vdd_ldo2,vdd_rtcO.Oldo3vdd_ldo3,avdd_usb*2Z.2Zldo4vdd_ldo4,avdd_osc,vddio_sysw@.w@ldo5vdd_ldo5,vcore_mmc+|.+|ldo6vdd_ldo6,avdd_vdac+|.+|ldo7vdd_ldo7,avdd_hdmi2Z.2Z"(ldo8vdd_ldo8,avdd_hdmi_pllw@.w@"(ldo9vdd_ldo9,vdd_ddr_rx,avdd_cam+|.+|ldo_rtc vdd_rtc_out2Z.2Ztemperature-sensor@4c onnn,nct1008gLspi@7000d400nvidia,tegra20-slinkgp k;v)})spi  rxtx disabledspi@7000d600nvidia,tegra20-slinkgp kRv,},spi  rxtx disabledspi@7000d800nvidia,tegra20-slinkgp kSv.}.spi  rxtx disabledspi@7000da00nvidia,tegra20-slinkgp k]vD}Dspi  rxtx disabledkbc@7000e200nvidia,tegra20-kbcgp kUv$}$kbc disabledpmc@7000e400nvidia,tegra20-pmcgp vnpclkclk32k_inF^r#memory-controller@7000f000nvidia,tegra20-mcgp$p< kMiommu@7000f024nvidia,tegra20-gartgp$Xmemory-controller@7000f400nvidia,tegra20-emcgpfuse@7000f800nvidia,tegra20-efusegpv'fuse}'fusepcie-controller@80003000nvidia,tegra20-pcie[pcig08 padsaficskbc intrmsi $b2xvFHvpexafipll_e}FHJpexafipcie_x disabled<=L`qpci@1,0[pcig disabledpci@2,0[pcig disabledusb@c5000000nvidia,tegra20-ehciusb-ehcig@ kutmiv}usb disabledusb-phy@c5000000nvidia,tegra20-usb-phyg@@utmi vjregpll_utimerutmi-pads}usbutmi-pads   5K ]q disabled"(usb@c5004000nvidia,tegra20-ehciusb-ehcig@@ kulpiv:}:usb disabledusb-phy@c5004000nvidia,tegra20-usb-phyg@@ulpiv:]regpll_uulpi-link}:usbutmi-pads disabled"(usb@c5008000nvidia,tegra20-ehciusb-ehcig@ kautmiv;};usbokayusb-phy@c5008000nvidia,tegra20-usb-phyg@@utmi v;jregpll_utimerutmi-pads};usbutmi-pads   5K ]qokay"(sdhci@c8000000nvidia,tegra20-sdhcig kv}sdhci disabledsdhci@c8000200nvidia,tegra20-sdhcig kv } sdhci disabledsdhci@c8000400nvidia,tegra20-sdhcig kvE}Esdhci disabledsdhci@c8000600nvidia,tegra20-sdhcig kv}sdhciokay : ;cpuscpu@0[cpuarm,cortex-a9gcpu@1[cpuarm,cortex-a9gpmuarm,cortex-a9-pmuk89i2cmuxi2c-mux-pinctrl ddcptaidlei2c@0g"(i2c@1gclocks simple-busclock@0 fixed-clockgk "(regulators simple-busregulator@1regulator-fixedg vdd_1v05. "(regulator@100regulator-fixedgdvcc_24vn6.n6"(regulator@101regulator-fixedgevdd_5v0LK@.LK@" ( regulator@102regulator-fixedgfvdd_3v32Z.2Z"(regulator@103regulator-fixedggvdd_1v8w@.w@"(backlightpwm-backlight LK@  @"(panel!innolux,n156bge-l21simple-panel, 9 F"(sound<ad,tegra-audio-wm8903-medcom-widenvidia,tegra-audio-wm8903PAvionic Design Medcom-Wide{]Headphone JackHPOUTRHeadphone JackHPOUTLInt SpkROPInt SpkRONInt SpkLOPInt SpkLONMic JackMICBIASIN1LMic Jackr  vpq^pll_apll_a_out0mclk #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathrtc0rtc1serial0device_typereginterruptsclocksresetsreset-namesrangesclock-namesnvidia,headstatusnvidia,panelvdd-supplypll-supplynvidia,ddc-i2c-busnvidia,hpd-gpiointerrupt-controller#interrupt-cellslinux,phandlearm,data-latencyarm,tag-latencycache-unifiedcache-level#clock-cells#reset-cells#dma-cells#gpio-cellsgpio-controllerpinctrl-namespinctrl-0nvidia,pinsnvidia,functionnvidia,pullnvidia,tristatedmasdma-namesreg-shift#pwm-cellsclock-frequencymicdet-cfgmicdet-delaygpio-cfgti,system-power-controllersys-supplyvin-sm0-supplyvin-sm1-supplyvin-sm2-supplyvinldo01-supplyvinldo23-supplyvinldo4-supplyvinldo678-supplyvinldo9-supplyregulator-nameregulator-always-onregulator-min-microvoltregulator-max-microvoltnvidia,invert-interruptnvidia,suspend-modenvidia,cpu-pwr-good-timenvidia,cpu-pwr-off-timenvidia,core-pwr-good-timenvidia,core-pwr-off-timenvidia,sys-clock-req-active-highreg-namesinterrupt-namesinterrupt-map-maskinterrupt-mapbus-rangeavdd-pex-supplyavdd-pex-pll-supplyavdd-plle-supplyvddio-pex-clk-supplyassigned-addressesnvidia,num-lanesphy_typenvidia,has-legacy-modenvidia,needs-double-resetnvidia,phynvidia,hssync-start-delaynvidia,idle-wait-delaynvidia,elastic-limitnvidia,term-range-adjnvidia,xcvr-setupnvidia,xcvr-lsfslewnvidia,xcvr-lsrslewnvidia,has-utmi-pad-registerscd-gpioswp-gpiosbus-widthi2c-parentpinctrl-1pinctrl-2enable-active-highvin-supplypwmsbrightness-levelsdefault-brightness-levelpower-supplyenable-gpiosbacklightnvidia,modelnvidia,audio-routingnvidia,i2s-controllernvidia,audio-codecnvidia,spkr-en-gpiosnvidia,hp-det-gpios