Π ώνβ80(²ψ$rockchip,rk3228-evbrockchip,rk3228&!7Rockchip RK3228 Evaluation boardchosenaliases=/serial@11010000E/serial@11020000M/serial@11030000memoryUmemorya`@cpuscpu@f00Ucpuarm,cortex-a7ael s€B@}œ@‹’˜cpu@f01Ucpuarm,cortex-a7ae’˜cpu@f02Ucpuarm,cortex-a7ae’˜cpu@f03Ucpuarm,cortex-a7ae’˜amba arm,amba-bus pdma@110f0000arm,pl330arm,primecella@§²‹Β ½apb_pclkarm-pmuarm,cortex-a7-pmu0§LMNOΙtimerarm,armv7-timerά0§   n6oscillator fixed-clockn6xin24m#’˜syscon@11000000syscona’˜serial@11010000snps,dw-apb-uarta §7n6‹MU½baudclkapb_pclk0default > HR _disabledserial@11020000snps,dw-apb-uarta §8n6‹NV½baudclkapb_pclk0default> HR _disabledserial@11030000snps,dw-apb-uarta §9n6‹OW½baudclkapb_pclk0default> HR_okaypwm@110b0000rockchip,rk3288-pwma f‹^½pwm0default>  _disabledpwm@110b0010rockchip,rk3288-pwma f‹^½pwm0default>  _disabledpwm@110b0020rockchip,rk3288-pwma f‹^½pwm0default> _disabledpwm@110b0030rockchip,rk3288-pwma 0f‹^½pwm0default> _disabledtimer@110c0000rockchip,rk3288-timera  §+ ‹a ½timerpclkclock-controller@110e0000rockchip,rk3228-cruaq#~‹›#gΈ€’˜dwmmc@30020000rockchip,rk3288-dw-mshca0@ §<4`°€<4` ‹ΛGuy½biuciuciu_drvciu_sampleΓ͞βμ0default >_okayχ +interrupt-controller@32010000 arm,gic-4009N a22 2@ 2`  § ’˜pinctrlrockchip,rk3228-pinctrlq gpio0@11110000rockchip,gpio-banka §3‹@_o9Ngpio1@11120000rockchip,gpio-banka §4‹A_o9Ngpio2@11130000rockchip,gpio-banka §5‹B_o9Ngpio3@11140000rockchip,gpio-banka §6‹C_o9Npcfg-pull-up{pcfg-pull-downˆpcfg-pull-none—’˜emmcemmc-clk€’˜emmc-cmd€’˜emmc-bus8€€’˜pwm0pwm0-pin€’ ˜ pwm1pwm1-pin€’ ˜ pwm2pwm2-pin€ ’˜pwm3pwm3-pin€ ’˜uart0uart0-xfer €’˜uart0-cts€’˜uart0-rts€’ ˜ uart1uart1-xfer €  ’ ˜ uart1-cts€uart1-rts€ uart2uart2-xfer €’ ˜ uart2-cts€uart2-rts€ #address-cells#size-cellscompatibleinterrupt-parentmodelserial0serial1serial2device_typeregresetsoperating-pointsclock-latencyclockslinux,phandlerangesinterrupts#dma-cellsclock-namesinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthstatus#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratesclock-freq-min-maxbus-widthdefault-sample-phasenum-slotsfifo-depthbroken-cdcap-mmc-highspeedmmc-ddr-1_8vdisable-wpnon-removableinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disablerockchip,pins